DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election of species A (figs. 1-9), reflected in claims 1, 3-7, 9-10 and 14-20 in the reply filed on 05/27/2026 is acknowledged. Claims 2, 8 and 11-13 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 9-10, 14 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by You et al. (US 20230187439 A1, hereinafter You’439).
Regarding independent claim 1, You’439 teaches, “A semiconductor device (fig. 1-16; ¶ [0001] - ¶ [0251]), comprising:
a lower pattern (BP1, fig. 2) extending primarily in a first direction (DR1), and comprising a first sidewall (sidewall of element 105, fig. 11) and a second sidewall (BP1_SW1) opposite to the first sidewall in a second direction (DR2);
a channel isolation structure (160ST, figs. 1, 11) extending primarily in the first direction (DR1) and in contact with a first sidewall of the lower pattern (BP1);
a field insulating layer (105) in contact with the second sidewall of the lower pattern (BP1);
a gate structure (115, 215, figs. 4, 11) disposed on the lower pattern (BP1), the gate structure being in contact with the channel isolation structure (160ST), and extending primarily in the second direction (DR2);
a channel pattern (NS1, NS2) disposed on the lower pattern (BP1), and comprising a plurality of sheet patterns (NS1, NS2) spaced apart from one another in a third direction (DR3), each of the plurality of sheet patterns (NS1, NS2, fig. 11) being in contact with the channel isolation structure (160ST); and
a source/drain pattern (150, fig. 2) in contact with both the channel pattern (NS1) and the channel isolation structure (160ST),
wherein the channel isolation structure (160ST, fig. 11) comprises a first region in contact with the gate structure (115, 215) and a second region in contact with the source/drain pattern (150), wherein the second region of the channel isolation structure (160ST) comprises a first portion and a second portion whose widths increase in the second direction (DR2) as a distance from a bottom surface of the field insulating layer (105) increases, wherein the second portion of the second region of the channel isolation structure (160ST) is disposed on the first portion of the second region of the channel isolation structure, and wherein a width of an uppermost portion of the channel isolation structure (160ST) in the first portion of the second region of the channel isolation structure is greater than a width of a lowermost portion of the channel isolation structure (160ST) in the second portion of the second region of the channel isolation structure”.
Regarding claim 3, You’439 further teaches, “The semiconductor device of claim 1, wherein a width of the channel isolation structure (160ST, figs. 1, 11) in the second direction (DR2) in the first region of the channel isolation structure continuously increases as the distance from the bottom surface of the field insulating layer (105) increases”.
Regarding claim 4, You’439 further teaches, “The semiconductor device of claim 1, wherein a height from the bottom surface of the field insulating layer (105) to an uppermost portion of the first portion of the second region of the channel isolation structure (160ST) is smaller than a height from the bottom surface of the field insulating layer to an uppermost portion of the source/drain pattern (150)”.
Regarding claim 5, You’439 further teaches, “The semiconductor device of claim 4, wherein a part of the source/drain pattern (150) overlaps the first portion of the second region of the channel isolation structure (160ST) in the third direction (DR3)”.
Regarding claim 6, You’439 further teaches, “The semiconductor device of claim 1, wherein a height from the bottom surface of the field insulating layer (150) to an uppermost portion of the first portion of the second region of the channel isolation structure (160ST) is smaller than a height from the bottom surface of the field insulating layer (150) to an upper surface of the channel pattern (NS1, NS2)”.
Regarding claim 7, You’439 further teaches, “The semiconductor device of claim 1, wherein each of the first portion of the second region of the channel isolation structure (160ST, figs. 1, 11) and the second portion of the second region of the channel isolation structure (160ST, figs. 1, 11) comprises a width center line extending primarily in the third direction (DR3), and wherein the width center line of the first portion of the second region of the channel isolation structure is aligned with the width center line of the second portion of the second region of the channel isolation structure in the third direction (DR3)”.
Regarding claim 9, You’439 further teaches, “The semiconductor device of claim 1, further comprising a lower insulating pattern (130, fig. 11) disposed between the lower pattern (BP1) and the channel pattern (NS1, NS2), and in contact with an upper surface of the lower pattern (BP1)”.
Regarding claim 10, You’439 further teaches, “The semiconductor device of claim 1, wherein a depth from an upper surface of the lower pattern (BP1, fig. 11) to a lowermost portion of the channel isolation structure (160ST) is smaller than or equal to a depth from the upper surface of the lower pattern (BP1) to the bottom surface of the field insulating layer (105)”.
Regarding claim 14, You’439 further teaches, “The semiconductor device of claim 1, further comprising a gate isolation structure (145) disposed on the field insulating layer (105), and extending primarily in the first direction (DR1), wherein the gate structure (115, 215) and the source/drain pattern (150) are each disposed between the channel isolation structure (160ST) and the gate isolation structure (145)”.
Regarding independent claim 19, You’439 teaches, “A semiconductor device (fig. 1-16; ¶ [0001] - ¶ [0251]), comprising:
a lower pattern (BP1, fig. 2) extending primarily in a first direction (DR1), and comprising a first sidewall (sidewall of element 105, fig. 11) and a second sidewall (BP1_SW1) opposite to the first sidewall in a second direction (DR2);
a channel isolation structure (160ST, figs. 1, 11) extending primarily in the first direction (DR1) and in contact with a first sidewall of the lower pattern (BP1);
a field insulating layer (105) in contact with the second sidewall of the lower pattern (BP1);
a gate isolation structure (130) disposed on the field insulating layer (105), and extending primarily in the first direction (DR1);
a gate structure (120) disposed between the channel isolation structure (160ST) and the gate isolation structure (130), and in contact with each of the channel isolation structure (160ST) and the gate isolation structure (130);
a channel pattern (NS1, NS2) disposed on the lower pattern (BP1), and comprising a plurality of sheet patterns (NS1, NS2) spaced apart from one another in a third direction (DR3), each of the plurality of sheet patterns (NS1, NS2, fig. 11) being in contact with the channel isolation structure (160ST); and
a source/drain pattern (150) disposed between the channel isolation structure (160ST) and the gate isolation structure (120), and in contact with each of the channel pattern (NS1, NS2) and the channel isolation structure (160ST),
wherein a part of the source/drain pattern (150) overlaps the channel isolation structure (160ST) in the third direction (DR3), and is disposed across the channel isolation structure (160ST)”.
Regarding claim 20, You’439 further teaches, “The semiconductor device of claim 19, wherein the channel isolation structure (160ST) comprises a first region in contact with the gate structure (120), and a second region in contact with the source/drain pattern (150), wherein the second region of the channel isolation structure (160ST) comprises a first portion and a second portion whose widths increase in the second direction as a distance from a bottom surface of the field insulating layer (105) increases, wherein the second portion of the second region of the channel isolation structure (160ST) is disposed on the first portion of the second region of the channel isolation structure (160ST), and wherein a width of an uppermost portion of the channel isolation structure (160ST) in the first portion of the second region of the channel isolation structure (160ST) is greater than a width of a lowermost portion of the channel isolation structure (160ST) in the second portion of the second region of the channel isolation structure (160ST)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over You’439 in view of Kwak et al. (US 20180090493 A1, hereinafter Kwak’493).
Regarding independent claim 15, You’439 teaches, “A semiconductor device (fig. 1-16; ¶ [0001] - ¶ [0251]), comprising:
a first gate structure (115, figs. 2, 1, A-A cross-section in fig. 1, near AP1) comprising a first gate electrode (120) and a first gate insulating layer (130);
a second gate structure (215, figs. 2, 1, A-A cross-section in fig. 1, near AP2) comprising a second gate electrode (220) and a second gate insulating layer (230), and spaced apart from the first gate structure in a first direction (DR2, figs. 1, 4);
a first source/drain pattern (150) disposed adjacent to the first gate structure (115) in a second direction (DR1, figs. 1, 2, A-A cross-section in fig. 1);
a second source/drain pattern (150) disposed adjacent to the second gate structure in the second direction (DR1, figs. 1, 2, A2-A2 cross-section in fig. 1), and spaced apart from the first source/drain pattern (150) in the first direction (DR2, fig. 1);
a channel isolation structure (160ST, figs. 1, 11) disposed between the first gate structure (115) and the second gate structure (215) and between the first source/drain pattern (on A-A in fig. 1) and the second source/drain pattern (on A2-A2 in fig. 1),
the channel isolation structure (160ST, fig. 1) extending primarily in the second direction (DR1);
a first channel pattern (NS1, fig. 11) comprising a plurality of first sheet patterns, each of the first sheet patterns being in contact with the channel isolation structure (160ST) and the first source/drain pattern (150, figs. 1-2); and
a second channel pattern (NS2, fig. 11) comprising a plurality of second sheet patterns, each of the second sheet patterns being in contact with the channel isolation structure (160ST) and the second source/drain pattern (150, figs. 1-2),
((wherein a width of the channel isolation structure between the first gate structure and the second gate structure in the first direction is different from a width of the channel isolation structure in the first direction between the first source/drain pattern and the second source/drain pattern))”.
But You’439 is silent upon the provision of wherein a width of the channel isolation structure between the first gate structure and the second gate structure in the first direction is different from a width of the channel isolation structure in the first direction between the first source/drain pattern and the second source/drain pattern.
However, Kwak’493 teaches a similar structure (fig. 2), wherein a width of the channel isolation structure (170, 160) between the first gate structure (115) and the second gate structure (215) in the first direction is different from a width of the channel isolation structure (160) in the first direction between the first source/drain pattern (150) and the second source/drain pattern (250).
You’439 and Kwak’493 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify You’439 with the features of Kwak’493 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of You’439 and Kwak’493 to form the channel isolation structure according to the teachings of Kwak’493 with a motivation ‘to effectively suppress short channel effect (SCE), which is a phenomenon in which the electric potential of a channel region is influenced by the drain voltage’. See Kwak’493, ¶ 0002.
Regarding claim 16, You’439 modified with Kwak’493 further teaches, “The semiconductor device of claim 15, wherein a width of the channel isolation structure (160, 170, fig. 2, Kwak’493) between the first gate structure and the second gate structure in the first direction is greater than a width of the channel isolation structure between the first source/drain pattern and the second source/drain pattern in the first direction”.
Regarding claim 17, You’439 modified with Kwak’493 further teaches, “The semiconductor device of claim 15, wherein each of the first gate insulating layer, the second gate insulating layer, the first source/drain pattern, and the second source/drain pattern are in contact with the channel isolation structure (You’439, fig. 11)”.
Regarding claim 18, You’439 modified with Kwak’493 further teaches, “The semiconductor device of claim 15, wherein the first source/drain pattern overlaps the channel isolation structure by a first width in the second direction, and wherein the second source/drain pattern overlaps the channel isolation structure by a second width different from the first width in the second direction (You’439, fig. 11 with fig. 2, Kwak’493)”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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