Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 03/19/2025. Currently, claims 1-3, 9-10, 13, 21, 23 and 25-36 are pending in the application. Claims 4-8, 11-12, 14-20, 22 and 24 have been cancelled. Claims 25-36 have been added new.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 21 and 23 are rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding clam Claim 21, wherein it recites the limitation "The semiconductor device package of claim 26” in line 1, wherein claim 21 cannot depend on claim 26 since a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed
Regarding clam Claim 23, this claim is rejected as it depends on claim 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 9-10, 13 and 28-36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SONG et al (US 20170092594 A1) in view of LEE et al (US 20160379961 A1) as an evidence for recess in the substrate.
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Regarding claim 1, Figure 5 (please see the annotated Figure above for labels) of SONG discloses a semiconductor device package, comprising:
a substrate (SB, [0048]) having a lower surface (LS);
a first insulation layer (IN1) disposed on the lower surface of the substrate and having a first surface (S1) facing away from the substrate; and
a first electrical contact (EC1) disposed on the lower surface of the substrate;
wherein the first electrical contact has a first portion under an elevation of the first surface of the first insulation layer;
a first electronic component (252, [0060]) disposed on a recessed surface ( recess in the substrate is not shown but anticipates to have recess for pad similar to the pad under solder ball to attach the solder balls shown between lower surface of the substrate and the die 252, please see Figure 4 of LEE wherein pads 12 are formed by recessing the surface of the substrate to bond 64, [0042]) formed in the lower (LS) surface of the substrate; and
a second electronic component (E2/212, [0050]) disposed on and abutting the lower surface of the substrate; wherein the first insulation layer (IN1) has an inclined surface (IS) adjacent to first electrical contact, wherein the first electrical contact (EC1) is disposed between the first electronic component (E1) and the second electronic component (E2).
Regarding claim 2, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 1, wherein the inclined surface (IS) extends from the first surface (S1) of the first insulation layer to the first electrical contact (EC1), and wherein the inclined surface defines a cavity (for EC1) accommodating the first electrical contact (EC1), and wherein a depth of the cavity is at least half of a thickness of the first insulation layer (IN1).
Regarding claim 3, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 2, inclined surface (IS) defines a cavity accommodating the first electrical contact (EC1), and wherein a width of the cavity is greater than a thickness of the first insulation layer (considering taking the width of EC1 in horizontal direction and the thickness of IN1 in vertical direction at a lower thick portion in the Figure) .
Regarding claim 9, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 1, wherein the first insulation layer comprises (IN1) a filler (FL) exposed by the first surface of the first insulation layer (filler is not defined in the claim and hence a layer such as FL exposed from the surface meets the limitation on a broadest reasonable interpretation).
Regarding claim 10, Figure 5 (please see the annotated Figure above for labels) of SONG discloses a semiconductor device package, comprising:
a substrate (SB) having a lower surface (LS);
a first electrical contact (EC1) disposed on the lower surface of the substrate;
a second electrical contact (EC2) disposed on the lower surface of the substrate;
a first electronic component (252) disposed on the lower surface of the substrate; and
a first insulation layer (IN1) encapsulating the lower surface of the substrate, the first and second electrical contacts and the first electronic component;
wherein the first insulation layer (IN1) has a first inclined surface (IS) facing and adjacent to the first electrical contact (EC1) and a second inclined surface (IS) facing and adjacent to the second electrical contact (EC2);
wherein the first electronic component (252) is not disposed between the first electrical contact (EC1) and the second electrical contact (EC2).
Regarding claim 13, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 10, further comprising a second electronic component (250) disposed on an upper surface of the substrate, wherein a thickness of the second electronic component (250) is different from a thickness of the first electronic component (252).
Regarding claim 28, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 2, wherein the first electrical contact (EC1) comprises a second portion defining a maximum cross-sectional width of the first electrical contact and positioned at a vertical location between the lower surface of the substrate (SB) and the cavity.
Regarding claim 29, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 28, wherein a cross-sectional width of the first electrical contact (EC1) gradually decreases from the second portion to the first portion.
Regarding claim 30, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 10, wherein a horizontal distance between the first electrical contact (EC1) and a lateral surface (left lateral side surface) of the substrate is less than a horizontal distance between the second electrical contact (EC2) and the lateral surface of the substrate (SB), and wherein the first electronic component (252) is positioned at a horizontal location between the first electrical contact and the lateral surface of the substrate.
Regarding claim 31, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 30, wherein the first electrical contact (EC1) has a first portion abuts the lower surface of the substrate and a second portion defining a maximum cross-sectional width of the first electrical contact, and wherein the first electronic component (252, [0060]) overlaps with the first inclined surface (IS) and the first and second portions of the first electrical contact in a direction substantially parallel to the lower surface of the substrate.
Regarding claim 32, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 13, wherein the second electronic component (250) overlaps with the first electronic component (252) in a direction substantially perpendicular to the lower surface of the substrate (SB).
Regarding claim 33, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 32, wherein a horizontal distance between the first electronic component (252) and a lateral surface of the substrate (SB) is less than a horizontal distance between the second electronic component (250) and the lateral surface of the substrate.
Regarding claim 34, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 33, wherein the second electronic component (250) does not overlap with the first electrical contact (EC1) in the direction substantially perpendicular to the lower surface of the substrate (SB).
Regarding claim 35, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 32, further comprising a third electronic component (224) is disposed on the upper surface of the substrate, wherein the third electronic component overlaps with the first and second inclined surfaces (IS) in the direction substantially perpendicular to the lower surface of the substrate.
Regarding claim 36, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 35, wherein a thickness of the third electronic component (224) is less than a thickness (in horizontal direction) of the second electronic component (250).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 25-27 are rejected under 35 U.S.C. 103 as being obvious over SONG et al (US 20170092594 A1) in view of Chen et al (US 20140185264 A1).
Regarding claim 25, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 1, wherein the first electronic components (252) have a lower surface exposed at the first surface (S1) of the first insulation layer (IN1) but does not teach that the second electronic component (212) has a lower surface covered by the first insulation layer.
However, Chen is a pertinent art which teaches a package or a package-on-package device for operation in high frequency, wherein die 301 is exposed but die 305 is not exposed from an insulating layer 113 and size is different from each other in ([0011] and [0017]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device package as claimed in order to form a package with high frequency operation according to the teaching of Chen ([0011] and [0017]).
Regarding claim 26, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 25, further comprising a third electronic component (202) disposed on an upper surface (US) of the substrate (SB), wherein a horizontal distance between a lateral surface (left side surface) of the substrate and the third electronic component (202) is greater than a horizontal distance between the lateral surface of the substrate and the second electronic component.
Regarding claim 27, Figure 5 (please see the annotated Figure above for labels) of SONG discloses that the semiconductor device package of claim 26, further comprising: a fourth electronic component (224) disposed on the upper surface (US) of the substrate and spaced apart from the third electronic component (250); and a second electrical contact (EC2) disposed under the substrate; wherein a horizontal distance between the third electronic component (250) and the fourth electronic component (224) is less than a horizontal distance between the first electrical contact (EC1) and the second electrical contact (EC2).
Claims 21 and 23 are rejected under 35 U.S.C. 103 as being obvious over SONG et al (US 20170092594 A1) in view of in view of Chen et al (US 20140185264 A1), and further in view of CHEN et al (US 20170221859 A1).
Regarding claims 21 and 23, Figure 5 of SONG does not teach that the semiconductor device package of claim 26, further comprising a conductive layer covering the first, second and third electronic components, wherein the conductive layer overlaps with the inclined surface in a direction substantially parallel to the first surface of the first insulation layer, wherein the second electronic component overlaps with the conductive layer in the direction.
However, CHEN is a pertinent art which teaches a semiconductor device includes a semiconductor die, an insulative layer, a conductive feature and a shield. The insulative layer surrounds the semiconductor die, and the insulative layer has a first surface and a second surface opposite to each other. The conductive feature is extended from the first surface to be proximal to the second surface of the insulative layer, and the conductive feature has a first end exposed by the first surface of the insulative layer. The shield covers the first surface of the insulative layer and is grounded through the first end of the conductive feature exposed by the first surface of the insulative layer ([0019]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device package as claimed in order to form a package with grounding by a conductive shield to remove Electromagnetic Interference ([0017] and [0019] of CHEN).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims 1-3, 9-10, 13, 21, 23 and 25-36, filed on 03/19/2025, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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