DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 9-20) in the reply filed on 05/23/2026 is acknowledged.
Claims 1-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/23/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Semiconductor Device With Bit Line Extending Non-Linearly”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2015/0340313 A1; hereinafter, “Choi”).
Regarding claims 9-20:
re claim 9, Choi discloses a semiconductor device comprising:
a substrate 100 (Fig. 32B);
an isolation layer 110 (Fig. 32B and [0033]) formed over the substrate and defining a plurality of active regions Ac (Figs. 32A-32B and [0032]);
a bit line contact plug DC (Fig. 32A and [0032]) coupled to a portion of the active regions Ac [0032]; and
a bit line 200C (Fig. 32B and [0088]) formed over the bit line contact plug,
wherein the bit line includes:
first line portions that intersect with the active regions (e.g., in Figs. 32A-32B, a first line portion would be a portion 200C directly above the dotted circle, DC in Fig. 32A, and directly below 205C in Fig. 32B); and
second line portions that extend in a direction different from a direction of the first line portions and overlap with the isolation layer 110 (i.e., the bit lines 200C in Fig. 32B are directly below insulating capping line 205C, and in Fig. 31A, line 205C, which corresponds to bit line 200C, has a zigzag shape such that a second line portion extends in a different direction from that of the first line).
re claim 10, the semiconductor device of claim 9, further comprising:
a gate trench 113 (Fig. 32B and [0037] formed in the active region Ac (Fig. 32B); and
a buried word line 120 (Fig. 32B and [0037]) formed in the gate trench;
re claim 11, the semiconductor device of claim 9, further comprising:spacer structures 240C (Figs. 32A-32B) formed on both sidewalls of the bit line 200C;
re claim 12, the semiconductor device of claim 9, wherein both sidewalls of the bit line 200C (Fig. 32A-32B, wherein bit line 200C corresponds to capping line 205C) have non-linearity in a direction that the bit line extends;
re claim 13, the semiconductor device of claim 9, wherein the first line portions and the second line portions are alternately arranged in a direction that the bit line extends (i.e., in Fig. 32A, the bit lines 200C, which are underneath line 205C, zigzag in the extending direction);
re claim 14, the semiconductor device of claim 9, wherein the first line portions and the second line portions include a same material (i.e., the bit lines are made of the same layer 200 in Fig. 2B and [0044]);
re claim 15, the semiconductor device of claim 9, wherein the first line portions and the second line portions have a same width and length (e.g., the zigzag portions in Fig. 32A have a same width and length);
re claim 16, the semiconductor device of claim 9, further comprising:
a bit line contact plug DC (Fig. 32A and [0032]) disposed below the bit line 200C (Figs. 32A-32B); and
a bit line hard mask 205C (Fig. 32B and [0081]) over the bit line contact plug DC (Fig. 32A),
wherein the bit line hard mask 205C has a same shape as a shape of the bit line 200C (Fig. 32B);
re claim 17, the semiconductor device of claim 9, wherein the bit line 200C (which is directly beneath line 205C in Figs. 32A-32B) includes a zigzag shape in which the first line portions and the second line portions are alternately arranged (Fig. 32A);
re claim 18, the semiconductor device of claim 9, further comprising:
storage node contact plugs 310 (Fig 14A in combination with Figs. 14B, 32A, 32B) neighboring the second line portions (i.e., the plugs 310 neighbor at least the second line portions),
wherein the storage node contact plugs 310 are coupled to edges of the active regions Ac (Fig. 14A);
re claim 19, the semiconductor device of claim 9, wherein the second line portions and the active regions Ac have non-overlapping directions (in Figs. 32A-32B, the active regions Ac and the zigzag pattern of “200C/205C” have non-overlapping directions); and
re claim 20, A semiconductor device comprising:
a plurality of active regions Ac (Fig. 32A-32B) separated by an isolation layer 110 (Fig. 32B; and
a bit line stacked structure 200C/205C coupled to at least portions of the active regions Ac (Fig. 32A);
wherein the bit line stacked structure comprises a non-linear bit line 200C which includes a plurality of alternating first and second line segments (e.g., in Fig. 32A, see zigzag pattern of 205C, which corresponds to bit line 200C in Fig. 32B), and
wherein the first and second line segments extend in a first and a second direction respectively (i.e., in a zigzag direction).
Therefore, Choi anticipates claims 9-20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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