DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see remarks, filed 07/24/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 102/103 have been fully considered and are persuasive, The amendments made overcome the rejection as written by the examiner in non-final rejection filed 04/24/2026 in view of the interview with the attorney, summary filed 06/12/2026 and the annotation of the insulating patterns for claim 18 as matched by the examiner in non-final rejection filed 04/24/2026. In view of the amendments made the examiners interpretation as presented in prior office action would at least no longer match the limitations of claim 18 which is dependent upon the independent claims. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made incorporating US 20190198668 A1 Tang et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10, 12, and 16-17 are rejected under 35 U.S.C. 35 U.S.C. 103 as obvious over US 20190067303 A1 Juengling et al hereafter “Juengling” in view of US 20190198668 A1 Tang et al hereafter “Tang”.
Claim 1 Juengling teaches a semiconductor device (device 10 as illustrated in the cross-sections of fig. 1-6), comprising:
a first bit line (comprising one of column 301-304, fig. 1, sufficiently illustrated as a bit line fig. 5, met under broadest reasonable interpretation of “bitline”) that extends in a first direction (top to bottom of fig. fig. 1 and 5, left to right fig. 3 and 4);
a first active pillar (comprising one of a set of 22, 24 and 26 of the first bit line fig. 3 and 4) and a second active pillar (comprising a different one of a set of 22, 24 and 26 of the first bit line fig. 3 and 4) on the first bit line [sufficiently illustrated fig. 1-5, where under broadest reasonable interpretation “On” includes the meaning/use of “a function word to indicate position in close proximity with” Merriam Webster dictionary];
a first gate insulating pattern (comprising one of a set of 28, 30, 31 contacting the first active pillar fig. 3-4) on the first active pillar; a second gate insulating (comprising one of a set of 28, 30, 31 contacting the second active pillar fig. 3-4) pattern the second active pillar;
a first word line (comprising one of row 201-203 comprising 14a-14b fig. 1-5) and a second word line (comprising a different one of row 201-203 comprising 14a-14b fig. 1-5) that extend in a second direction (left to right fig. 1, 2 and 5,) that intersects the first direction [sufficiently illustrated fig. 1 and 5]; and
a protection pattern (comprising a portion of 31 between the worlines fig. 3-4) between the first and second word lines [sufficiently illustrated fig. 3-4], wherein an air gap [not illustrated but sufficiently disclosed wherein the protection pattern consists of a composition comprising void spaces (air gaps) Paragraph 0045 “Insulator material 48 (e.g., about 24 nm thickness) is shown as electrical isolation between immediately-adjacent vias 42 and such may also include one or more void spaces (not shown). Materials 45 and/or 48 may be of the same composition relative one another and/or relative insulator materials 30 and/or 31”] is between the first and second word lines and is adjacent the protection pattern [sufficiently met wherein the void spaces (air gaps) are within the protection pattern 31].
In the alternative, even if Juengling is not considered to explicitly teach the air gap as claimed, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Juengling in view of the void spaces and/or air gaps taught by Juengling such that “ an air gap is between the first and second word lines and is adjacent the protection pattern” to assist the protection pattern in isolating adjacent conductive structures [See Paragraph 0045 Juengling].
Juengling does not teach the first gate insulating pattern enclosing the first active pillar; The second gate insulating pattern enclosing the second active pillar in the context of the rest of the claims.
Tang teaches a first gate insulating pattern [a first 46 fig. 16] enclosing a first active pillar [a first 22 contacting the first gate insulating pattern fig. 16];
a second gate insulating pattern [a second 46 fig. 16] enclosing a second active pillar [a second 22 contacting the second gate insulating pattern fig. 16].
Tang also teaches a known alternative wherein the first gate insulating pattern [a first 46 fig. 11] does not enclose the first active pillar [a first 22 contacting the first gate insulating pattern fig. 11];
the second gate insulating pattern [a second 46 fig. 11] does not enclose the second active pillar [a second 22 contacting the second gate insulating pattern fig. 11].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jingling in view of Tang such that the “first gate insulating pattern enclosing the first active pillar” and the “second gate insulating pattern enclosing the second active pillar in the context of the rest of the claims”.
A person of ordinary skill in the art would have been motivated to make this modification to enable a gate wrap around structure to enable strong coupling between the gates and the channel regions during operation of the transistors [Tang Paragraph 0013]
In addition, substituting and/or combining art recognized equivalents for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is gate structures for the same purpose of electrically addressing vertical channel structures.
Claim 2 modified Juengling in view of Tang teaches as shown above the semiconductor device of claim 1, wherein each of the first and second active pillars has a tetragonal or rectangular shape (sufficiently disclosed fig. 6), and wherein a width the first active pillar of in the first direction [see annotation below] is less than a width of the first active pillar in the second direction [see annotation below] [sufficiently illustrated fig. 6].
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Annotated fig. 6: highlighting widths
Claim 3 modified Juengling in view of Tang teaches as shown above the semiconductor device of claim 1, further comprising: an insulating structure (comprising 48 fig. 3, illustrated not labeled fig. 4) on the first word line, the second word line, and the protection pattern [best illustrated fig. 3], wherein the insulating structure is between the first and second gate insulating patterns [met under broadest reasonable interpretation as at least part of the insulating structure crosses the space between the first and second word lines fig. 3].
Claim 4 modified Juengling in view of Tang teaches as shown above the semiconductor device of claim 3, wherein the insulating structure comprises: a first vertical portion [see annotation below] in contact with a top surface of the first word line [best illustrated fig. 3]; a second vertical portion [see annotation below] in contact with a top surface of the second word line [best illustrated fig. 3];; and a horizontal portion [see annotation below] connecting the first and second vertical portions to each other, wherein a distance of a top surface of the horizontal portion from a substrate is greater than respective distances of respective top surfaces of each of the first and second word lines from the substrate [sufficiently illustrated fig. 3].
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Annotated fig. 3: highlighting portions
Claim 5 modified Juengling in view of Tang teaches as shown above the semiconductor device of claim 4, wherein the first vertical portion of the insulating structure is between the first active pillar and the protection pattern [sufficiently illustrated fig. 3], and wherein the second vertical portion of the insulating structure is between the second active pillar and the protection pattern [sufficiently illustrated fig. 3].
Claim 6 Modified Juengling in view of Tang teaches as shown above the semiconductor device of claim 1, wherein the first gate insulating pattern comprises:
a first sidewall [see annotation below, 28 in contact with 14a fig. 3-4] that extends in the first direction;
a second sidewall [see annotation below, 31 and/or 30 fig. 2] that extends in the second direction;
a third sidewall [see annotation below, 28 in contact with 14b fig. 3-4] spaced apart from the first sidewall in the second direction; and,
a fourth sidewall [see annotation below, 30 and/or 31 fig. 2] spaced apart from the second sidewall in the first direction
wherein the first, and third sidewalls of the first gate insulating pattern are in contact with the first word line [sufficiently illustrated fig. 1-5, best illustrated fig. 3-4].
the second and fourth sidewalls of the first gate insulating pattern are in contact with the first worldline [met in view of the modification of Tang, and the wrap around grate structure as illustrated fig. 16, wherein the wordlines/gates 50 wrap around all four sides of the insulating patterns 46 enclosing the semiconductor pillar 22].
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Juengling Annotated fig. 6: highlighting the location of the sidewall from a top down view
Claim 10 Juengling in view of Tang teaches as shown above the semiconductor device of claim 1, further comprising: a second bit line (comprising one of 301-304 fig. 1, sufficiently illustrated as a bit line fig. 5, comprising 36 of 301-304 fig. 2-4) spaced apart from the first bit line in the second direction [sufficiently illustrated fig. 1]; a third active pillar on the second bit line [sufficiently disclosed in view of the cross sections as illustrated fig. 1-6]; and an insulating pillar between the first and third active pillars, wherein the first gate insulating pattern is on the first active pillar, the third active pillar, and the insulating pillar in plan view [sufficiently disclosed/illustrated in view of the cross sections as illustrated fig. 1-6].
Claim 12 Juengling teaches a semiconductor device (fig. 1-5 represent various cross-section of the semiconductor device), comprising:
a first bit line (comprising one of columns 301-304 fig. 1-5) that extends in a first direction (up to down fig. 1 and fig. 5, left to right fig. 3 and 4);
a first active pillar (Comprising one set of 22, 24, 26 of the first bit line fig. 3 and 4) and a second active pillar (comprising one set of 22, 24, 26 of the second bit line fig. 3 and 4) on the first bit line [sufficiently illustrated fig. 1-5, wherein under broadest reasonable interpretation “on” includes the meaning/use of “a function word to indicate position in close proximity with” Merriam Webster dictionary];
a first gate insulating pattern (a portion of 28, 30, 31 contacting the first active pillar fig. 3 and 4) on the first active pillar [sufficiently illustrated fig. 3 and 4]; a second gate insulating pattern (a portion of 28, 30, 31 contacting the second active pillar fig. 3 and 4) on the second active pillar [sufficiently illustrated fig. 3 and 4]; a first word line (comprising one of 201-203 comprising 14a and 14b fig. 1-5) and a second word line (comprising a different one of 201-203 comprising 14a and 14b fig. 1-5) that extend in a second direction (left to right fig. 1 and 5) that intersects the first direction; and
a protection pattern (comprising 31 and 48 fig. 3-4) between the first and second word lines, wherein the protection pattern comprises a first portion (sufficiently illustrated fig. 3-4, see annotation below) in contact with the first word line and a second portion (sufficiently illustrated fig. 3-4, see annotation below) in contact with the second word line, and wherein an air gap [not illustrated but sufficiently disclosed wherein the protection pattern consists of a composition comprising void spaces (air gaps) Paragraph 0045 “Insulator material 48 (e.g., about 24 nm thickness) is shown as electrical isolation between immediately-adjacent vias 42 and such may also include one or more void spaces (not shown). Materials 45 and/or 48 may be of the same composition relative one another and/or relative insulator materials 30 and/or 31”] is between the first and second portions of the protection pattern.
In the alternative, even if Juengling is not considered to explicitly teach the air gap as claimed, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Juengling in view of the void spaces and/or air gaps taught by Juengling such that “ an air gap is between the first and second portions of the protection pattern” to assist the protection pattern in isolating adjacent conductive structures [See Paragraph 0045 Juengling].
Juengling does not teach the first gate insulating pattern enclosing the first active pillar; The second gate insulating pattern enclosing the second active pillar in the context of the rest of the claims.
Tang teaches a first gate insulating pattern [a first 46 fig. 16] enclosing a first active pillar [a first 22 contacting the first gate insulating pattern fig. 16];
a second gate insulating pattern [a second 46 fig. 16] enclosing a second active pillar [a second 22 contacting the second gate insulating pattern fig. 16].
Tang also teaches a known alternative wherein the first gate insulating pattern [a first 46 fig. 11] does not enclose the first active pillar [a first 22 contacting the first gate insulating pattern fig. 11];
the second gate insulating pattern [a second 46 fig. 11] does not enclose the second active pillar [a second 22 contacting the second gate insulating pattern fig. 11].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jingling in view of Tang such that the “first gate insulating pattern enclosing the first active pillar” and the “second gate insulating pattern enclosing the second active pillar in the context of the rest of the claims”.
A person of ordinary skill in the art would have been motivated to make this modification to enable a gate wrap around structure to enable strong coupling between the gates and the channel regions during operation of the transistors [Tang Paragraph 0013]
In addition, substituting and/or combining art recognized equivalents for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is gate structures for the same purpose of electrically addressing vertical channel structures.
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Annotated fig. 3: highlighting the portions
Claim 16 Juengling in view of Tang teaches as shown above the semiconductor device of claim 12, further comprising:
a second bit line (comprising a different one of 301-304 fig. 1, sufficiently illustrated as a bit line fig. 5) spaced apart from the first bit line in the second direction [best illustrated fig. 1 and 5]; a third active pillar (comprising a set of 22, 24, and 26 of the second pit line fig. 3-4, in view of the device as illustrated fig. 1 and 5) and a fourth active pillar (comprising a set of 22, 24, and 26 of the second bit line fig. 3-4, in view of the device as illustrated fig. 1 and 5) on the second bit line [sufficiently illustrated in view of the device as illustrated fig. 1 and 5]; and a third gate insulating pattern (left 28 fig. 3-4 in view of the device as illustrated fig. 1 and 5) and a fourth gate insulating pattern (right 28 fig. 3-4 in view of the device as illustrated fig. 1 and 5) on the third and fourth active pillars [sufficiently illustrated fig. 3-4 in view of the device as illustrated fig. 1 and 5], respectively, wherein the first gate insulating pattern is in contact with the third gate insulating pattern, and wherein the second gate insulating pattern is in contact with the fourth gate insulating pattern [sufficiently illustrated fig. 3-4 in view of the device as illustrated fig. 1 and 5].
Claim 17 Juengling in view of Tang teaches as shown above the semiconductor device of claim 12, wherein a width of the first portion of the protection pattern [see annotation below] in the first direction is less than a width of the first active pillar [see annotation below] in the first direction [sufficiently illustrated fig. 3-4].
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Annotated fig. 3 highlighting widths in the first direction
Claims 7-9, and 11 under 35 U.S.C. 103 as obvious over Juengling in view of Tang as shown above and in further view of US 10629732 B1 Sills et al hereafter “Sills”.
Claim 7 Modified Juengling teaches the semiconductor device of claim 1,
Juengling does not teach wherein each of the first and second active pillars has an elliptical shape.
Sills teaches that elliptical shape active pillars (channels) are art recognized equivalents and/or alternatives to rectangular active pillars (channels) [sufficiently disclosed column 4 lines 44-44 “Channel region 24 is shown as being rectangular in horizontal cross-section although other shapes may of course be used (e.g., any polygon, a structure have curved sides [e.g., a circle, ellipse, etc.], a combination of curved and straight sides, etc.)” ].
It would have been obvious to one of ordinary skill in the art to modify the first and second active pillars in view of the teachings of Sills such that “each of the first and second active pillars has an elliptical shape” as substituting equivalents known for the same purpose is prima facie type obviousness [2144.06 II] and/or changes in shape are prima type obviousness [2144.04 IV B.]
Claim 8 Modified Juengling in view of Sills teaches as shown above the semiconductor device of claim 7, wherein the first word line comprises an outer side surface in contact with the protection pattern [sufficiently illustrated fig. 1-5, best illustrated fig. 3], and wherein the outer side surface of the first word line has a curved shape [necessarily met in view of the modification of Sills as the worldines and protection patterns are illustrated as conformal to the active pillars, Juengling fig. 1-5 and Sills fig. 1-2 ].
Claim 9 Juengling in view of Sills as shown above the semiconductor device of claim 8, wherein the protection pattern (Juengling a portion of 31 between the world lines fig. 1-5, in view of the modification of Sills sufficiently discloses the embodiment comprising 45 fig. 8-9) comprises an exposed surface defining the air gap (sufficiently disclosed by Juengling as shown in claim 1, in view of Sills 48 fig. 8-9), and wherein the exposed surface of the protection pattern has a curved shape [necessarily met in view of the modification of Juengling as shown above as the air gap is conformal with the world lines, the gate insulation, and the active pillars].
Should the applicant disagree it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shape of the exposed surface of the protection pattern with air gap such that “and wherein the exposed surface of the protection pattern has a curved shape” as a part of routine optimization of the insulation between adjacent world lines provide by the air gap and protective pattern [see MPEP 2144.05 II.] and/or as changes in is shape are prima facie type obviousness [see MPEP 2144.04 IV B.].
Claim 11 Juengling teaches the semiconductor device of claim 1,
Juengling does not teach wherein a length of the air gap in the second direction is greater than respective lengths of each of the first and second gate insulating patterns in the second direction.
Sills teaches a length [see annotation below] of an air gap (48 fig. 8-9) in a second direction (left to right fig. 8) is greater than respective lengths [see annotation below] of each of a first and second gate insulating patterns (36 fig. 8-9) in the second direction [sufficiently illustrated fig. 8-9].
It would have been obvious to one of ordinary skill in the art before the effective to combine the airgap as taught by Juengling with the airgap as taught by Sills such that “a length of the air gap in the second direction is greater than respective lengths of each of the first and second gate insulating patterns in the second direction” to ensure continuous isolation between adjacent word lines, and/or as a part of routine optimization of the isolation provide by the airgap to adjacent world lines [See MPEP 2144.05 II.] and/or combining/substituting equivalents known for the same purpose is prima facie type obviousness, in this case airgaps [2144.06]
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Sills annotated fig. 8: highlighting lengths
Claims 13 and 18-20 under 35 U.S.C. 103 as obvious over Juengling in view of Tang as shown above and in further view of US 20150243748 A1 Pulugurtha et al hereafter “Pulugurtha”
Claim 13 Juengling teaches as shown above the semiconductor device of claim 12, wherein the protection pattern further comprises a third portion [a top portion fig. 3-4 see annotation above] connecting the first and second portions to each other [best illustrated fig. 3], wherein the first and second portions of the protection pattern are adjacent to side surfaces of the air gap [necessarily met in view of the air gap as shown in claim 12], and wherein the third portion of the protection pattern is on a top surface of the air gap [necessarily met in view of the air gap as shown in claim 12].
Alternatively In the case the applicant disagrees with the structure of the air gap as shown above, Pulugurtha teaches a protection pattern (140 fig. 1H) that horizontally separates a first conductive feature ( left 146 fig. 1H) and a second conductive feature (right 146 fig. 1H) comprising a first portion [see annotation below] in contact with the first conductive feature, a second portion [see annotation below] in contact with the second conductive feature, an air gap (152 fig. 1H) is between the first and second portions of the protection pattern; wherein the protection pattern further comprises a third portion [see annotation below] connecting the first and second portions to each other [sufficiently illustrated fig. 1H], wherein the first and second portions of the protection pattern are adjacent to side surfaces of the air gap [sufficiently illustrated fig. 1H], and wherein the third portion of the protection pattern is on a top surface of the air gap [sufficiently illustrated fig. 1H].
It would have been obvious to one of ordinary skill in the art to combine the protection pattern and airgaps of Juengling with the protection pattern and air gaps of Pulugurtha such that “the first and second portions of the protection pattern are adjacent to side surfaces of the air gap, and wherein the third portion of the protection pattern is on a top surface of the air gap” to limit capacitance and increase shorts margin between gate electrodes of neighboring vertical access devices and to reduce cross-talk between neighboring vertical access devices [Paragraph 0057 Pulugurtha] and/or to provide the associated dielectric constant of the air gaps for to isolate adjacent conductive components [Sufficiently disclosed paragraph 0056 Pulugurtha “he open volumes 152 provides insulators having a dielectric constant (c) of about 1”] and/or combining equivalences known for the same purpose (in this case protective/isolation patterns for isolating adjacent conductive components) is prima facie type obviousness [see MPEP 2144.06].
Claim 18 Juengling in view of Pulugurtha teaches as shown above the semiconductor device of claim 13, further comprising:
a third gate insulating pattern (left 28 fig. 3-4 in view of the device as illustrated fig. 1, 5 and 6) spaced apart from the first gate insulating pattern in the second direction [sufficiently disclosed in view of the device as illustrated fig. 1-6]; and a fourth gate insulating pattern (right 28 fig. 3-4 in view of the device as illustrated fig. 1, 5 and 6)) spaced apart from the second gate insulating pattern in the second direction [sufficiently disclosed in view of the device as illustrated fig. 1-6], wherein the first word line comprises a first intervening portion between the first and third gate insulating patterns [met in view of the modification of Tang and the wrap around gate structure 50 as illustrated fig. 16, see annotation below], and wherein the second word line comprises a second intervening portion [see annotation below] between the second and fourth gate insulating patterns [met in view of the modification of Tang and the wrap around gate structure 50 as illustrated fig. 16].
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Annotated fig. 16 Tang; highlighting intervening portions
Claim 19 Juengling teaches a semiconductor device, comprising:
a first bit line (comprising one of column 301, 302, 303 fig. 1-5, met under broadest reasonable interpretation) and a second bit line (comprising a different one of column 301, 302, 303 fig. 1-5, met under broadest reasonable interpretation) that extend in a first direction (up to down fig. 1 and 5, left to right fig. 3-4);
a first word line (comprising one of rows 201, 202, 203 comprising 14a-14b fig. 1-5) and a second word line (comprising a different one of rows 201, 202, 203 comprising 14a-14b fig. 1-5) that extend in a second direction (left to right fig. 1, 2 and 5 ) that intersects the first direction [sufficiently illustrated fig. 1-5];
a first active pillar (comprising one of 75 comprising 22,26, and 24 on the first bit line fig. 1-5) and a second active pillar (comprising a different one of 75 comprising 22,26, and 24 on the first bit line fig. 1-5) on the first bit line [sufficiently illustrated fig. 1-5];
a third active pillar (comprising one of 75 comprising 22,26, and 24 on the second bit line fig. 1-5) and a fourth active pillar (comprising a different one of 75 comprising 22,26, and 24 on the second bit line fig. 1-5) on the second bit line;
a data contact (comprising 34 fig. 1-5, met under broadest reasonable interpretation and/or MPEP 2112) electrically connected to each of the first, second, third, and fourth active pillars [sufficiently illustrated fig. 1-5];
a landing pad (comprising 38 fig. 1-5, met under broadest reasonable interpretation and/or MPEP 2112) electrically connected to the data contact [sufficiently illustrated fig. 1-5];
a data storage pattern (comprising 40 fig. 1-5, met under broadest reasonable interpretation and/or MPEP 2112) electrically connected to the landing pad [sufficiently illustrated fig. 1-5];
a first gate insulating pattern, a second gate insulating pattern, a third gate insulating pattern, and a fourth gate insulating pattern (comprising 28,30, and 31 contacting the respective active pillars, sufficiently illustrated fig. 1-5) on the first, second, third, and fourth active pillars, respectively [sufficiently illustrated fig. 1-5];
a protection pattern (comprising a horizontal portion 31 between the worldlines fig. 1-5) between the first and second word lines [sufficiently illustrated fig. 1-5, best illustrated fig. 3]; and
an insulating structure (comprising 48 fig. 1-5) on the first word line, the second word line, and the protection pattern [sufficiently illustrated fig. 1-5, best illustrated fig. 3], wherein the first word line is on the first and third gate insulating patterns [sufficiently illustrated fig. 1-5], wherein the second word line is on the second and fourth gate insulating patterns [sufficiently illustrated fig. 1-5], wherein the protection pattern comprises:
a first portion (a first side of 31 contacting 14a or 14b and between 14a and 14b fig. 1-5, best illustrated fig. 3) in contact with the first word line [sufficiently illustrated fig. 1-5]; a second portion (a second side of 31 contacting 14a or 14b and between 14a and 14b fig. 1-5) in contact with the second word line [sufficiently illustrated fig. 1-5]; and a third portion (a portion of 31 between the first and second sides of fig. 31 fig. 1-5) connecting the first and second portions to each other [sufficiently illustrated fig. 1-5],
wherein the first, second, and third portions of the protection pattern define an air gap
[sufficiently disclosed as having a composition comprising and air gap and/or void space paragraph 0045, “Insulator material 48 (e.g., about 24 nm thickness) is shown as electrical isolation between immediately-adjacent vias 42 and such may also include one or more void spaces (not shown). Materials 45 and/or 48 may be of the same composition relative one another and/or relative insulator materials 30 and/or 31” under broadest reasonable interpretation of “define” which includes the meaning “to fix or mark the limits of”(Merriam-Webster Dictionary) wherein if the air gap is part of and/or whole within the protection pattern the portions of the protection pattern must mark the limits of the air gap].
Alternatively In the case the applicant disagrees with the structure of the air gap as shown above, Pulugurtha teaches a protection pattern (140 fig. 1H) that horizontally separates a first conductive feature ( left 146 fig. 1H) and a second conductive feature (right 146 fig. 1H) comprising a first portion [see annotation below] in contact with the first conductive feature, a second portion [see annotation below] in contact with the second conductive feature, an air gap (152 fig. 1H) is between the first and second portions of the protection pattern; wherein the protection pattern further comprises a third portion [see annotation below] connecting the first and second portions to each other [sufficiently illustrated fig. 1H], wherein the first and second portions of the protection pattern are adjacent to side surfaces of the air gap [sufficiently illustrated fig. 1H], and wherein the third portion of the protection pattern is on a top surface of the air gap [sufficiently illustrated fig. 1H].
It would have been obvious to one of ordinary skill in the art to combine the protection pattern and airgaps of Juengling with the protection pattern and air gaps of Pulugurtha such that “the first and second portions of the protection pattern are adjacent to side surfaces of the air gap, and wherein the third portion of the protection pattern is on a top surface of the air gap” to limit capacitance and increase shorts margin between gate electrodes of neighboring vertical access devices and to reduce cross-talk between neighboring vertical access devices [Paragraph 0057 Pulugurtha] and/or to provide the associated dielectric constant of the air gaps to isolate adjacent conductive components [Sufficiently disclosed paragraph 0056 Pulugurtha “he open volumes 152 provides insulators having a dielectric constant (c) of about 1”] and/or combining equivalences known for the same purpose (in this case protective/isolation patterns for isolating adjacent conductive components) is prima facie type obviousness [see MPEP 2144.06].
Juengling does not teach “the first gate insulating pattern, the second gate insulating pattern, the third gate insulating pattern, and the fourth gate insulating pattern enclosing the first, second, third, and fourth active pillars, respectively” in the context of the rest of the claim limitations.
Tang teaches the first gate insulating pattern, the second gate insulating pattern, the third gate insulating pattern, and the fourth gate insulating pattern (insulating patterns 46 fig. 16) enclosing the first, second, third, and fourth active pillars (the respective active pillars 22 fig. 16), respectively [sufficiently illustrated fig. 16].
Tang additionally teaches a known alternative wherein the first gate insulating pattern, the second gate insulating pattern, the third gate insulating pattern, and the fourth gate insulating pattern (insulating patterns 46 fig. 11) do not enclose the first, second, third, and fourth active pillars (the respective active pillars 22 fig. 16), respectively [sufficiently illustrated fig. 11]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jingling in view of Tang such that the “the first gate insulating pattern, the second gate insulating pattern, the third gate insulating pattern, and the fourth gate insulating pattern enclosing the first, second, third, and fourth active pillars, respectively”.
A person of ordinary skill in the art would have been motivated to make this modification to enable a gate wrap around structure to enable strong coupling between the gates and the channel regions during operation of the transistors [Tang Paragraph 0013].
In addition, substituting and/or combining art recognized equivalents for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is gate structures for the same purpose of electrically addressing vertical channel structures.
Claim 20 Juengling in view of Pulugurtha and Tang teaches as shown above the semiconductor device of claim 19, wherein a distance [see annotation below] of the third portion of the protection pattern from a substrate (comprising 11 fig. 1-5) is greater than respective distance (see annotation below) of the first and second word lines to the substrate.
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Juengling Annotated fig. 3: highlighting distances
Claims 14-15 under 35 U.S.C. 103 as obvious over Juengling in view of Tang as shown above and in further view of US 20140110816 A1 Kim et al hereafter “Kim”.
Claim 14 Juengling in view of Tang teaches the semiconductor device of claim 12, further comprising:
Juengling does not explicitly teach a blocking pattern between the first and second portions of the protection pattern, wherein the blocking pattern has a top surface adjacent a bottom surface of the air gap.
Kim et al teaches a blocking pattern (20 fig. 15B) has a top surface [the top most surface] adjacent to a bottom surface [the bottom most surface] of an air gap (AG fig. 15B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modified the device of Juengling in view of the device of Kim suc that a “blocking pattern has a top surface adjacent a bottom surface of the air gap” to stop etching passed the blocking pattern when etching to forming the airgap and/or prevent damage to the device during cleaning/etching processes [sufficiently disclosed between Kim Paragraph 0073 “Since the first sub-spacer 23 and the etch stop pattern 20 may be formed of materials having an etch selectivity with respect to the natural oxide layer, they may not be etched. Further, since the etch stop patterns 20 may be formed to cover edge portions the second sub-spacers 21 in the storage node contact hole BH, it is possible to prevent the second sub-spacer 21 from being removed or damaged in the cleaning process used to remove the natural oxide layer” and paragraph 0085 “the spacer 30 may include the air-gap regions AG instead of the second sub-spacers 21”]
Claim 15 Juengling in view of Tang and Kim teaches the semiconductor device of claim 14,
Juengling in view of Tang and Kim does not explicitly teach wherein a distance from the top surface of the air gap to a substrate is greater than a distance of the first word line to the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Juengling in view of Kim such that “a distance from the top surface of the air gap to a substrate is greater than a distance of the first word line to the substrate” as a part of routine optimization of the insulation provide by air gap between the world lines and/or the active pillars [See MPEP 2144.05 II.] and/or changes in relative size and/or proportions is prima facie type obviousness [See MPEP 2144.04 IV A.]
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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