DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 3 and 11 are cancelled. Claims 1, 2, and 9 are amended. Claims 14-17 are new, no new matter is present. Claims 1-2, 4-10, and 12-17 are present for examination.
Response to Arguments
Applicant’s arguments, see page 7, filed July 01, 2026, with respect to the title objection has been fully considered and are persuasive. The title objection of April 02, 2026 has been withdrawn.
Applicant’s arguments, see page 7, filed July 01, 2026, with respect to the objection to claim 2 has been fully considered and are persuasive. The objection to claim 2 of April 02, 2026 has been withdrawn.
Applicant’s arguments, see pages 7-10, filed July 01, 2026, with respect to the rejection(s) of claim(s) 1-13 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Cho (US 2022/0384661 A1).
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the relative positioning of the source layer within each field-effect transistor as well as the geometry of the one or more branching-off webs in a top-down view of the xy-plane (e.g. wherein each source layer is disposed diagonally adjacent to a delimited region within the field-effect transistor further including one or more branching-off webs which are disposed on opposite sides of the source layer; Instant Application, Fig. 1). The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-10, 12-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec (US 2021/0408279 A1) in view of Cho (US 2022/0384661 A1).
Claim 1, Siemieniec discloses a semiconductor component (semiconductor device 500 is a semiconductor component, hereinafter, semiconductor component 500, [0108], Fig. 6), comprising:
a source layer doped according to a first type (source regions 110 is defined by the dopants contained in the source layer 710 according to a first type (i.e. n-type), hereinafter, source layer doped according to the first type 110, [0088], Figs. 1E and 6);
a drain layer doped according to the first type (drain/drift structure 130 includes a drift zone 131 according to the first type (i.e. n-type), hereinafter, drain layer doped according to the first type 130, [0088], Figs. 1E and 6);
a channel layer (body regions 120 is a channel layer, hereinafter, channel layer 120, [0105], Fig. 7) located vertically between the source layer doped according to the first type 110 and the drain layer doped according to the first type 130 (channel layer 120 is located vertically between the source layer doped according to the first type 110 and the drain layer doped according to the first type 130, [0105], Fig. 7);
a gate trench (trench gate structure 150 is a gate trench, hereinafter, gate trench 150, [0114], Fig. 6), which extends vertically from the source layer doped according to the first type 110 to the drain layer doped according to the first type 130 (gate trench 150 extends vertically from the source layer doped according to the first type 110 to the drain layer doped according to the first type 130, [0114], Fig. 6) and adjoins the channel layer 120 and at least a portion of the source layer doped according to the first type 110 (gate trench 150 adjoins the channel layer 120 and at least a portion of the source layer doped according to the first type 110, [0114], Fig. 6);
a first shielding region doped according to a second type (top shielding region 161 is a first shielding region doped according to a second type (i.e. p-type), hereinafter, first shielding region doped according to a second type 161, [0117], Fig. 6), which extends vertically from the source layer doped according to the first type 110, or a semiconductor surface adjoining it (first surface 101 is a semiconductor surface adjoining the first shielding region doped according to a second type 161, hereinafter, semiconductor surface 101, [0117], Fig. 6), to the drain layer doped according to the first type 130 (first shielding region doped according to a second type 161 extends vertically from the source layer doped according to the first type 110 (or a semiconductor surface 101 adjoining it) to the drain layer doped according to the first type 130, [0117], Fig. 6);
a second shielding region doped according to the second type (buried shielding region 162 is a second shielding region doped according to the second type (i.e. p-type), hereinafter, second shielding region doped according to the second type 162, [0123], Fig. 6), which is arranged vertically below a bottom of the gate trench 150 (second shielding region doped according to the second type 162 is arranged vertically below a bottom of the gate trench 150, [0123], Fig. 6), wherein the gate trench 150 and the second shielding region doped according to the second type 162 are configured such that, in one or more delimited regions (i.e. drain/drift structure 130 is one or more delimited regions, hereinafter, drain layer doped according to the first type and delimited regions 130), the second shielding region doped according to the second type 162 extends horizontally at least to the first shielding region doped according to the second type 161 (gate trench 150 and the second shielding region doped according to the second type 162 are configured such that, in one or more delimited regions 130, the second shielding region doped according to the second type 162 extends horizontally (i.e. y-direction) at least to the first shielding region doped according to the second type 161, [0089], Fig. 6).
Siemieniec does not explicitly disclose wherein the gate trench and the second shielding region doped according to the second type are strip-shaped, as seen in a horizontal direction, with one or more branching-off webs, which extend to the one or more delimited regions.
However, Cho (US 2022/0384661 A1) discloses wherein the gate trench and the second shielding region doped according to the second type are strip-shaped, as seen in a horizontal direction, with one or more branching-off webs, which extend to the one or more delimited regions (Cho, gate trench T and the second shielding region 115 doped according to the second type are strip-shaped, as seen in a horizontal direction (i.e. D1), with one or more branching-off webs, which extend to the one or more delimited regions, [0024], Figs. 2A and 2B; Siemieniec, gate trench 150 and the second shielding region doped according to the second type 162 are strip-shaped, as seen in a horizontal direction (i.e. y-direction), with one or more branching-off webs, which extend to the one or more delimited regions 130, [0089], Fig. 6). The combination to utilize a second shielding region in addition to the gate trench, as well as resultant strip-shaped extensions within an adjacent delimited region wherein the channel layer may have a structure that overlaps the underlying region, so that current characteristics may be significantly improved, specifically, an ON-current (Ion) characteristic may be increased by 10 to 20 times (Cho, [0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a second shielding region in addition to the gate trench, as well as resultant strip-shaped extension within an adjacent delimited region wherein the channel layer may have a structure that overlaps the underlying region, so that current characteristics may be significantly improved, specifically, an ON-current (Ion) characteristic may be increased by 10 to 20 times (Cho, [0049]).
Claim 2, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho discloses wherein the semiconductor component is a transistor (Siemieniec, semiconductor component 500 is a transistor (i.e. insulated gate field effect transistor (IGBT)), [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 4, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho discloses wherein the second shielding region doped according to the second type is formed in the gate trench by implantation (Siemieniec, second shielding region doped according to the second type 162 is formed by implantation of second dopants through the spacer mask openings 425 within the gate trench 150, [0103], Figs. 4A-4B and 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 5, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho discloses wherein the drain layer doped according to the first type includes a drift layer doped according to the first type (Siemieniec, drain layer doped according to the first type 130 includes drift zone 131 according to the first type (i.e. n-type), hereinafter, drift layer doped according to the first type 131, [0088], Figs. 1E and 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) and a spread layer doped according to the first type (Siemieniec, current spread regions 137 is a spread layer doped according to the first type, hereinafter, spread layer doped according to the first type 137, [0105], Fig. 7; Cho, semiconductor device 100, [0022], Figs. 2A and 2B), wherein the spread layer doped according to the first type is more highly doped than the drift layer doped according to the first type and adjoins the channel layer (Siemieniec, spread layer doped according to the first type 137 is more highly doped than the drift layer doped according to the first type 131 and adjoins the channel layer 120, [0128], Fig. 7; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 6, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho discloses wherein the channel layer is doped according to the second type (i.e. p-type) at least partially (Siemieniec, channel layer 120 is doped according to the second type (i.e. p-type) at least partially, [0122], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 7, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho discloses further comprising:
a gate electrode (Siemieniec, gate electrode 155, [0114], Fig. 6) which has a conductive gate electrode material (Siemieniec, gate electrode 155 has a conductive gate electrode material (i.e. ), [0114], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) at least partially surrounded by a dielectric (Siemieniec, gate electrode 155 is at least partially surrounded by a dielectric (i.e. gate dielectric 159), [0114], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B), and which is introduced into the gate trench (Siemieniec, gate electrode 155 is at least partially surrounded by a dielectric 159 which is introduced into the gate trench 150, [0114], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 8, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho discloses wherein the semiconductor component is a SiC or GaN or gallium-oxide field-effect transistor (Siemieniec, semiconductor component 500 is a silicon carbide (SiC) field-effect transistor (i.e. insulated gate field effect transistor (IGBT)), [0109], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 9, Siemieniec discloses a method for producing a semiconductor component (semiconductor device 500 is a semiconductor component, hereinafter, method of forming semiconductor component 500, [0108], Figs. 1A-1G), comprising the following steps:
providing a starting material (silicon carbide body 100 is a starting material, hereinafter, starting material 100, [0071], fig. 1A) including:
a source layer doped according to a first type (source regions 110 is defined by the dopants contained in the source layer 710 according to a first type (i.e. n-type), hereinafter, source layer doped according to the first type 110, [0088], Figs. 1E and 6), a drain layer doped according to the first type (drain/drift structure 130 includes a drift zone 131 according to the first type (i.e. n-type), hereinafter, drain layer doped according to the first type 130, [0088], Figs. 1E and 6), on a substrate doped according to the first type (silicon carbide body 100 includes lightly n-doped drift zone 131 which may serve as a substrate doped according to the first type (i.e. n-type), hereinafter, substrate doped according to the first type 131, [0076], Fig. 1A), and a channel layer (body regions 120 is a channel layer, hereinafter, channel layer 120, [0105], Fig. 7) located vertically between the source layer doped according to the first type 110 and the drain layer doped according to the first type 130 (channel layer 120 is located vertically between the source layer doped according to the first type 110 and the drain layer doped according to the first type 130, [0105], Fig. 7);
forming a first shielding region doped according to a second type (top shielding region 161 is a first shielding region doped according to a second type (i.e. p-type), hereinafter, first shielding region doped according to a second type 161, [0117], Fig. 6), which extends vertically from the source layer doped according to the first type 110, or a semiconductor surface adjoining it (first surface 101 is a semiconductor surface adjoining the first shielding region doped according to a second type 161, hereinafter, semiconductor surface 101, [0117], Fig. 6), to the drain layer doped according to the first type 130 (first shielding region doped according to a second type 161 extends vertically from the source layer doped according to the first type 110 (or a semiconductor surface 101 adjoining it) to the drain layer doped according to the first type 130, [0117], Fig. 6);
forming a gate trench (trench 450 is formed and is the same trench as the trench gate structure 150, hereinafter, gate trench 150/450, [0114], Fig. 6) which extends vertically from the source layer doped according to the first type 110 to the drain layer doped according to the first type 130 (gate trench 150 extends vertically from the source layer doped according to the first type 110 to the drain layer doped according to the first type 130, [0114], Fig. 6) and adjoins the channel layer 120 and at least a portion of the source layer doped according to the first type 110 (gate trench 150/450 adjoins the channel layer 120 and at least a portion of the source layer doped according to the first type 110, [0114], Fig. 6); and
forming a second shielding region doped according to the second type (buried shielding region 162 is a second shielding region doped according to the second type (i.e. p-type), hereinafter, second shielding region doped according to the second type 162, [0123], Fig. 6), vertically below a bottom of the gate trench 150/450 (second shielding region doped according to the second type 162 is arranged vertically below a bottom of the gate trench 150/450, [0123], Fig. 6);
wherein the gate trench 150/450 and the shielding region doped according to the second type 162 are configured in such a way that, in one or more delimited regions (i.e. drain/drift structure 130 is one or more delimited regions, hereinafter, drain layer doped according to the first type and delimited regions 130), the second shielding region doped according to the second type 162 extends horizontally at least to the first shielding region doped according to the second type 161 (gate trench 150/450 and the second shielding region doped according to the second type 162 are configured such that, in one or more delimited regions 130, the second shielding region doped according to the second type 162 extends horizontally (i.e. y-direction) at least to the first shielding region doped according to the second type 161, [0089], Fig. 6).
Siemieniec does not explicitly disclose wherein the gate trench and the second shielding region doped according to the second type are strip-shaped, as seen in a horizontal direction, with one or more branching-off webs, which extend to the one or more delimited regions.
However, Cho (US 2022/0384661 A1) discloses wherein the gate trench and the second shielding region doped according to the second type are strip-shaped, as seen in a horizontal direction, with one or more branching-off webs, which extend to the one or more delimited regions (Cho, gate trench T and the second shielding region 115 doped according to the second type are strip-shaped, as seen in a horizontal direction (i.e. D1), with one or more branching-off webs, which extend to the one or more delimited regions, [0024], Figs. 2A and 2B; Siemieniec, gate trench 150 and the second shielding region doped according to the second type 162 are strip-shaped, as seen in a horizontal direction (i.e. y-direction), with one or more branching-off webs, which extend to the one or more delimited regions 130, [0089], Fig. 6). The combination to utilize a second shielding region in addition to the gate trench, as well as resultant strip-shaped extensions within an adjacent delimited region wherein the channel layer may have a structure that overlaps the underlying region, so that current characteristics may be significantly improved, specifically, an ON-current (Ion) characteristic may be increased by 10 to 20 times (Cho, [0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a second shielding region in addition to the gate trench, as well as resultant strip-shaped extension within an adjacent delimited region wherein the channel layer may have a structure that overlaps the underlying region, so that current characteristics may be significantly improved, specifically, an ON-current (Ion) characteristic may be increased by 10 to 20 times (Cho, [0049]).
Claim 10, Siemieniec/Cho discloses the method (Siemieniec, method of forming semiconductor component 500, [0108], Figs. 1A-1G; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 9.
Siemieniec/Cho discloses wherein the semiconductor component is a transistor (Siemieniec, semiconductor component 500 is a transistor (i.e. insulated gate field effect transistor (IGBT)), [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 12, Siemieniec/Cho discloses the method (Siemieniec, method of forming semiconductor component 500, [0108], Figs. 1A-1G; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 9.
Siemieniec/Cho discloses wherein the gate trench is formed first (Siemieniec, gate trench 450 is formed first, [0079, Figs. 1A-1B; Cho, semiconductor device 100, [0022], Figs. 2A and 2B), and wherein the second shielding region doped according to the second type is formed after the gate trench is formed (Siemieniec, second shielding region doped according to the second type 162 is formed after the gate trench 150/450 is formed from second implant regions 762, [0086], Figs. 1A-1B and 1D; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 13, Siemieniec/Cho discloses the method (Siemieniec, method of forming semiconductor component 500, [0108], Figs. 1A-1G; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 9.
Siemieniec/Cho discloses wherein the second shielding region doped according to the second type is formed in the gate trench by implantation (Siemieniec, second shielding region doped according to the second type 162 is formed by implantation of second dopants through the spacer mask openings 425 within the gate trench 150/450, [0103], Figs. 4A-4B and 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 14, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 7.
Siemieniec/Cho discloses wherein the dielectric at the bottom of the gate trench has a greater thickness than the dielectric on the side walls of the gate trench (Cho, gate insulating layer 140 includes a bottom insulating portion 140C which is a dielectric at the bottom of the gate trench T, hereinafter, dielectric at the bottom of the gate trench 140C and has a greater thickness than the first gate insulating element 140A which is a dielectric on the side walls of the gate trench T, hereinafter, dielectric on the side walls of the gate trench 140A, [0036], Figs. 2A, 2B, and 7; Siemieniec, gate electrode 155 is at least partially surrounded by a dielectric 159 which is introduced into the gate trench 150, [0114], Fig. 6).
Claim 15, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho discloses wherein the gate trench and the one or more branching-off webs form a grid (Cho, gate trench T and the one or more branching-off webs 110 form a grid, [0076], Figs. 2A, 2B, and 12B; Siemieniec, semiconductor component 500, [0108], Fig. 6).
Claim 17, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 5.
Siemieniec/Cho discloses wherein the spread layer doped according to the first type extends vertically from the channel layer to below the first shielding region doped according to the second type (Siemieniec, spread layer doped according to the first type 137 extends vertically from the channel layer 120 to below the first shielding region doped according to the second type 161, [0105], Fig. 7; Cho, semiconductor device 100, [0022], Figs. 2A and 2B).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec in view of Cho, and further in view of Aichinger (US 2018/0331204 A1).
Claim 16, Siemieniec/Cho discloses the semiconductor component (Siemieniec, semiconductor component 500, [0108], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B) according to claim 1.
Siemieniec/Cho does not explicitly disclose wherein the first shielding region doped according to the second type is partially overdoped in its upper region by the source layer doped according to the first type.
However, Aichinger (US 2018/0331204 A1) discloses wherein the first shielding region doped according to the second type is partially overdoped in its upper region by the source layer doped according to the first type (Aichinger, first shielding region doped according to the second type 140/141 is partially overdoped in its upper region by the source layer doped according to the first type 110, [0098], Figs. 3A and 3B; Siemieniec, first shielding region doped according to a second type 161 is partially overdoped in its upper region by the source layer doped according to the first type 110, [0117], Fig. 6; Cho, semiconductor device 100, [0022], Figs. 2A and 2B). The combination to utilize a partially overdoped shielding region of the opposite conductivity type where in contact with the adjacent source layer results in an additional pn-junction with the resultant semiconductor device (Aichinger, [0098]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a partially overdoped shielding region of the opposite conductivity type where in contact with the adjacent source layer to result in an additional pn-junction with the resultant semiconductor device (Aichinger, [0098]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wong (US 2023/0021938 A1) discloses a semiconductor component (vertical transistor 200 is a semiconductor component, hereinafter, semiconductor component 200, [0018], Fig. 2A), wherein the semiconductor component 200 is a SiC or GaN or gallium-oxide field-effect transistor (semiconductor component 200 is a field-effect transistor comprising substrate 201 which may include SiC or GaN or gallium-oxide, [0018] and [0025], Fig. 2A).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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