Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 7, 2024 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--Semiconductor Devices Including A Routing Component Containing Deep Trench Capacitors Located Between Upper And Lower Redistribution Layers And Related Methods Of Manufacturing--
Claim Objections
Claims 2, 3, 5, 8, 9, 10, 11, 13, 16, 17, 18, and 20 are objected to because of the following informalities:
In all the claims objected to, “comprising” in the preamble should read --further comprising--.
In addition:
Claim 9: “underfill” should read --an underfill--
Claim 16: “The electronic device of claim 1” should read --The electronic device of claim 12--
Claim 17: “underfill” should read --an underfill--
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-20 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Lee et al. (U.S. Pub. 2022/0384308), hereinafter Lee..
Examiner notes that in the specification the Applicant defines “coupled” as “two elements indirectly connected by one or more other elements” and “can refer to an electrical coupling or a mechanical coupling.” See Paragraph [0014]. It is under this broad definition that the Examiner applies the interpretation of the prior art below.
Regarding Claim 1, Lee teaches an electronic device ((1g); Fig. 11A, Paragraph [0086]) comprising:
-a lower redistribution structure ((42); Fig. 11A, Paragraph [0066]) comprising a lower redistribution structure upper side (e.g. top of (42)) and a lower redistribution structure lower side (e.g. bottom of (42));
-an upper redistribution structure ((52); Fig. 11A, Paragraph [0067]) comprising an upper redistribution structure upper side (e.g. top of (52)) and an upper redistribution structure lower side (e.g. bottom of (52));
-a first electronic component ((61); Fig. 11A, Paragraph [0085]) coupled to the upper redistribution structure upper side (top of (52));
-a second electronic component ((62); Fig. 11A, Paragraph [0085]) coupled to the upper redistribution structure upper side (top of (52)); and
-a routing component ((2); Figs. 2 and 11A, Paragraph [0059]) comprising a routing redistribution structure ((11); Figs. 2 and 11A, Paragraph [0067]), a component die (‘DIE’ comprising (20) and (27); Figs. 2 and 11A, Paragraph [0060] and [0062]), component through-interconnects ((23); Fig. 8, Paragraph [0073]- Examiner notes that this is provided as an additional structure which while not shown explicitly in Figs. 2 and 11A, is present in the embodiment utilized by the Examiner), and a component encapsulant (comprising (12) and (29); Fig. 2 and 11A, Paragraph [0059] and [0064]); wherein
-the component encapsulant ((12) and (29)) comprises a component encapsulant upper side (e.g. top of (29)) and a component encapsulant lower side (e.g. (122)) (Paragraph [0065]); wherein
-the routing redistribution structure (11) comprises a routing redistribution structure upper side (top of (11)) coupled to the upper redistribution structure lower side (bottom of (52)) and a routing redistribution structure lower side (bottom of (11)) on the component encapsulant upper side (e.g. top of (29)) (as visible in Fig. 2); wherein
-the component die (‘DIE’) comprises a component die substrate (20) and a die interface structure (27) on the component die substrate (20); wherein the die interface structure (27) is coupled to the routing redistribution structure lower side (bottom of (11)); and wherein
-the component through-interconnects (23) extend through the component encapsulant ((12) and (29)) (necessarily, as (12) encapsulates it) and couple the routing redistribution structure lower side (bottom of (11)) to the lower redistribution structure upper side (top of (42)).
Regarding Claim 3, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 1, further comprising:
-die interconnects ((28); Fig. 2 and 11A, Paragraph [0062]) that couple the die interface structure (27) to the routing redistribution structure (11).
Regarding Claim 4, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 1, wherein:
-an upper surface of the component die substrate (top of (20)) comprises one or more passive elements (‘deep trench capacitors’ (25); Fig. 2 and 11A, Paragraph [0059]).
Regarding Claim 5, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 4, further comprising:
-die through-interconnects ((24); Figs. 2 and 11A, Paragraph [0060]) that extend through the component die substrate (20) and couple the lower redistribution structure (42) to the one or more passive elements (25).
Regarding Claim 6, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 4, wherein:
-the one or more passive elements (25) comprise one or more deep trench capacitors (Paragraph [0059]).
Regarding Claim 7, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 4, wherein:
-the one or more passive elements (25) are coupled to the die interface structure (27).
Regarding Claim 8, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 1, further comprising:
-an upper encapsulant ((16); Fig. 11A, Paragraph [0068]) that laterally surrounds the first electronic component (61) and the second electronic component (62).
Regarding Claim 9, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 8, further comprising:
-an underfill (e.g. top (51); Fig. 2 and 11A, Paragraph [0067]) between a lower side of the first electronic component (61) and the upper redistribution structure upper side (top of (52)).
Regarding Claim 10, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 1, further comprising:
-a lower encapsulant (e.g. right and left portions of (14); Fig. 11A, Paragraph [0065]) that laterally surrounds the routing component (2).
Regarding Claim 11, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 10 further comprising:
-device through-interconnects ((3); Fig. 11A, Paragraph [0063]) that pass through the lower encapsulant (14) and couple the upper redistribution structure (52) to the lower redistribution structure (42).
Regarding Claim 12, Lee teaches an electronic device ((1g); Fig. 11A, Paragraph [0086]) comprising:
-a lower redistribution structure ((42); Fig. 11A, Paragraph [0066]) comprising a lower redistribution structure upper side (e.g. top of (42)) and a lower redistribution structure lower side (e.g. bottom of (42));
-an upper redistribution structure ((52); Fig. 11A, Paragraph [0067]) comprising an upper redistribution structure upper side (e.g. top of (52)) and an upper redistribution structure lower side (e.g. bottom of (52));
-a first electronic component ((61); Fig. 11A, Paragraph [0085]) coupled to the upper redistribution structure upper side (top of (52));
-a second electronic component ((62); Fig. 11A, Paragraph [0085]) coupled to the upper redistribution structure upper side (top of (52)); and
-a component die (‘DIE’ comprising (20) and (27); Figs. 2 and 11A, Paragraph [0060] and [0062]), comprising a component die lower side (bottom of (‘DIE’)) coupled to the lower redistribution structure upper side (top of (42)) and a component die upper side (top of (‘DIE’)) coupled to the upper redistribution structure lower side (bottom of (52)); wherein
-the component die (‘DIE’) comprises a component die substrate (20), one or more passive elements (‘deep trench capacitors’ (25); Fig. 2 and 11A, Paragraph [0059]) along an upper surface of the component die substrate (top of (20)), a die interface structure ((27); Figs. 2 and 11A, Paragraph [0060] and [0062]) over the component die substrate (20) and the one of more passive elements (25), and die through-interconnects ((24); Figs. 2 and 11A, Paragraph [0060]) that pass through the component die substrate (20) and couple the one or more passive elements (25) to the lower redistribution structure (42).
Regarding Claim 13, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 12, further comprising:
-Die interconnects (comprising (28) and (11); Fig. 2 and 11A, Paragraph [0067]), that couple the die interface structure (27) to the upper redistribution structure (52).
Regarding Claim 14, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 12, wherein:
-the one or more passive elements (25) comprise one or more deep trench capacitors (Paragraph [0059]).
Regarding Claim 15, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 12, wherein:
-the one or more passive elements (25) are coupled to the upper redistribution structure (52).
Regarding Claim 16, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 12, further comprising:
-an upper encapsulant ((16); Fig. 11A, Paragraph [0068]) that laterally surrounds the first electronic component (61) and the second electronic component (62).
Regarding Claim 17, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 16, further comprising:
-an underfill (e.g. top (51); Fig. 2 and 11A, Paragraph [0067]) between a lower side of the first electronic component (61) and the upper redistribution structure upper side (top of (52)).
Regarding Claim 18, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 12, further comprising:
-a lower encapsulant (e.g. right and left portions of (14); Fig. 11A, Paragraph [0065]) that laterally surrounds the component die (‘DIE’).
Regarding Claim 19, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 18, further comprising:
-device through-interconnects ((3); Fig. 11A, Paragraph [0063]) that pass through the lower encapsulant (14) and couple the upper redistribution structure (52) to the lower redistribution structure (42).
Regarding Claim 20, Lee teaches a method of manufacturing an electronic device ((1g); Fig. 11A, Paragraph [0086]), the method comprising:
-providing a lower redistribution structure ((42); Fig. 11A, Paragraph [0066]) comprising a lower redistribution structure upper side (e.g. top of (42)) and a lower redistribution structure lower side (e.g. bottom of (42));
-providing an upper redistribution structure ((52); Fig. 11A, Paragraph [0067]) comprising an upper redistribution structure upper side (e.g. top of (52)) and an upper redistribution structure lower side (e.g. bottom of (52));
-providing a routing component ((2); Figs. 2 and 11A, Paragraph [0059]) on the lower redistribution structure upper side (top of (42)), wherein:
-the routing component (2) comprises a routing redistribution structure (‘RSS’ (comprising (28) and (11); Fig. 2 and 11A, Paragraph [0067]), a component die (‘DIE’ comprising (20) and (27); Figs. 2 and 11A, Paragraph [0060] and [0062]), component through-interconnects ((23); Fig. 8, Paragraph [0073]- Examiner notes that this is provided as an additional structure which while not shown explicitly in Figs. 2 and 11A, is present in the embodiment utilized by the Examiner), and a component encapsulant (comprising (12) and (29); Fig. 2 and 11A, Paragraph [0059] and [0064]);
-the component encapsulant ((12) and (29)) comprises a component encapsulant upper side (e.g. top of (29)) and a component encapsulant lower side (e.g. (122)) (Paragraph [0065]); wherein
-the routing redistribution structure (‘RSS’) comprises a routing redistribution structure upper side (top of (‘RSS’)) coupled to the upper redistribution structure lower side (bottom of (52)) and a routing redistribution structure lower side (bottom of (11)) on the component encapsulant upper side (e.g. top of (29)) (as visible in Fig. 2); wherein
-the component die (‘DIE’) comprises a component die substrate (20) and a die interface structure (27) on the component die substrate (20); wherein the die interface structure (27) is coupled to the routing redistribution structure lower side (bottom of (11)); and wherein
-the component through-interconnects (23) extend through the component encapsulant ((12) and (29)) (necessarily, as (12) encapsulates it) and couple the routing redistribution structure lower side (bottom of (11)) to the lower redistribution structure upper side (top of (42));
-providing a first electronic component ((61); Fig. 11A, Paragraph [0085]) coupled to the upper redistribution structure upper side (top of (52));
-providing a second electronic component ((62); Fig. 11A, Paragraph [0085]) coupled to the upper redistribution structure upper side (top of (52)); and
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding Claim 2, Lee teaches the electronic device ((1g); Fig. 11A, Paragraph [0086]) of Claim 1, but does not teach in the utilized embodiment:
-routing interconnects that couple the routing redistribution structure (11) to the upper redistribution structure (52).
Lee teaches in a separate embodiment (Fig. 10, Paragraph [0082]):
-routing interconnects ((18); Fig. 10, Paragraph [0073]) that couple the routing redistribution structure (11) to the upper redistribution structure (52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Lee into the device of Lee such that routing interconnects that couple the routing redistribution structure to the upper redistribution structure. This would be due to the fact that doing so would produce the predictable result of incorporating an alternative connection structure into the device, one with enchanced electrical connection (Paragraph [0076]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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