CTNF 18/440,178 CTNF 97153 DETAILED ACTION Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Regarding PCT Patent Application No. PCT/CN2024/071385 (filed 1/9/2024) Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Information Disclosure Statement The information disclosure statements submitted on 3/5/2024 and 9/29/2025 have been considered. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Regarding Step 1 of the Alice/Mayo framework, Claims 1-7 are directed to a processor (a machine), Claims 8-14 are directed to a system (a machine), and Claims 15-20 are directed to a method (a process), which each fall within one of the four statutory categories of inventions. Regarding Claim 1 Step 2A, prong 1 (Is the claim directed to a law of nature, a natural phenomenon or an abstract idea). Claim 1 recites the following mental processes, that in each case under the broadest reasonable interpretation, covers performance of the limitation in the mind (including an observation, evaluation, judgment, opinion) or with the aid of pencil and paper but for the recitation of generic computer components (e.g., “processor”, “circuits”, “neural network”). ... identify one or more first portions of first information to be used by the one or more neural networks to generate second information, ... (under the broadest reasonable interpretation, a human can mentally identify a first portion of first information to be input to a neural network to generate second information, such as identifying the amount of available memory capacity to be input into a NN to determine an optimal dataset size) ... identify the one or more first portions based, at least in part, on an amount of available storage. (under the broadest reasonable interpretation, a human can mentally identify a first portion of first information to be input to a neural network based at least in part on an amount of available memory capacity) Step 2A, prong 2 (Does the claim recite additional elements that integrate the judicial exception into a practical application?). The judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements (e.g., “processor”, “circuits”, “neural network”) which are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using a generic computer component (See MPEP 2106.05(f)). Regarding the “ processor ”, “ one or more circuits to cause one or more neural networks to ” and “ wherein the one or more neural networks are to ” limitations, such limitations are recited at a high-level of generality and amount to no more than adding the words “apply it” (or an equivalent) with the judicial exception. In particular, the claim only recites the additional elements of processors, circuits, and generic neural networks. These additional elements are recited at a high-level of generality and amount to no more than mere instructions to apply the exception using generic computer components (processors, circuits, and generic neural networks). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea (See MPEP 2106.05(f)). Accordingly, at Step 2A, prong two, after considering all claim elements individually and as an ordered combination, it is determined that the claims do not integrate the judicial exception into a practical application. Step 2B (Does the claim recite additional elements that amount to significantly more than the judicial exception?) In accordance with Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more that the judicial exception. As discussed above, the additional elements (e.g., “processor”, “circuits”, “neural network”) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using a generic computer component (See MPEP 2106.05(f)). Regarding the “ processor ”, “ one or more circuits to cause one or more neural networks to ” and “ wherein the one or more neural networks are to ” limitations, such limitation is recited at a high-level of generality and amounts to no more than adding the words “apply it” (or an equivalent) with the judicial exception, because the limitation merely provides instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. Accordingly, this additional element does not add significantly more than the judicial exception. (See MPEP 2106.05(f)). Accordingly, at Step 2B after considering all claim elements individually and as an ordered combination, it is determined that the claims do not integrate the judicial exception into a practical application. Regarding Claim 2 Step 2A, Prong 1 wherein the second information includes an expected relevance between the one or more first portions and one or more second portions. (under the broadest reasonable interpretation, this can be performed mentally by inferring the relevance between the one or more first portions and one or more second portions, such as by inferring the relevance between first portions of available memory capacity and second portions of available processing capacity) Regarding Step 2A, Prong 2 , the claim does not include any additional elements that integrate the judicial exception into a practical application and regarding Step 2B, there are no additional elements recited that amount to significantly more than the judicial exception. Regarding Claim 3 Step 2A, Prong 1 identify the one or more first portions based, at least in part, on an amount of available storage of a graphics processing unit (GPU). (under the broadest reasonable interpretation, a human can mentally identify a first portion of first information based on the amount of available memory capacity available through a GPU) Step 2A, Prong 2 Regarding the “ wherein the one or more neural networks are to ” limitation, such limitation is recited at a high-level of generality and amounts to no more than adding the words “apply it” (or an equivalent) with the judicial exception. In particular, the claim only recites the additional element of a neural network. This additional element is recited at a high-level of generality and amounts to no more than mere instructions to apply the exception using a generic computer component (a neural network). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea (See MPEP 2106.05(f)). Step 2B Regarding the “ wherein the one or more neural networks are to ” limitation, such limitation is recited at a high-level of generality and amounts to no more than adding the words “apply it” (or an equivalent) with the judicial exception, because the limitation merely provides instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. Accordingly, this additional element does not add significantly more than the judicial exception. (See MPEP 2106.05(f)). Regarding Claim 4 Step 2A, Prong 1 perform one or more matrix multiplication operations using information of the one or more first portions. (under the broadest reasonable interpretation, a human can write the first portions of information into a vector and perform matrix multiplication using pencil and paper; the examiner notes that matrix multiplication is also a specific mathematical calculation that is another type of abstract idea) Step 2A, Prong 2 Regarding the “ wherein the one or more circuits are to use the one or more neural networks to” limitation, such limitations are recited at a high-level of generality and amount to no more than adding the words “apply it” (or an equivalent) with the judicial exception. In particular, the claim only recites the additional elements of circuits and neural networks. These additional elements are recited at a high-level of generality and amount to no more than mere instructions to apply the exception using generic computer components (circuits and neural networks). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea (See MPEP 2106.05(f)). Step 2B Regarding the “ wherein the one or more circuits are to use the one or more neural networks to” limitation, such limitation is recited at a high-level of generality and amounts to no more than adding the words “apply it” (or an equivalent) with the judicial exception, because the limitation merely provides instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. Accordingly, this additional element does not add significantly more than the judicial exception. (See MPEP 2106.05(f)). Regarding Claim 5 Step 2A, Prong 1 wherein the one or more first portions comprise are represented using a data format dynamically selected based, at least in part, on the amount of available storage. (under the broadest reasonable interpretation, a human can dynamically select a particular data format for encoding the first portions, based at least in part on the amount of available storage, such as using Huffman coding if there is a lot of data storage available, and a different encoding scheme if there is only a little data storage available) Regarding Step 2A, Prong 2 , the claim does not include any additional elements that integrate the judicial exception into a practical application and regarding Step 2B, there are no additional elements recited that amount to significantly more than the judicial exception. Regarding Claim 6 Step 2A, Prong 1 wherein the amount of available storage is based, at least in part, on one or more allocations to a GPU shared storage. (under the broadest reasonable interpretation, a human can mentally determine the available memory based on shared allocations of GPU storage available) Regarding Step 2A, Prong 2 , the claim does not include any additional elements that integrate the judicial exception into a practical application and regarding Step 2B, there are no additional elements recited that amount to significantly more than the judicial exception. Regarding Claim 7 Step 2A, Prong 1 wherein the first information is represented using a tile data format (under the broadest reasonable interpretation, a human can represent data using a tile data format, such as drawing squares on a piece of paper and putting data in each square, or tile) Step 2A, Prong 2 Regarding the “ of one or more buffers to be stored in a shared memory ” limitation, such limitations are recited at a high-level of generality and amount to no more than adding the words “apply it” (or an equivalent) with the judicial exception. In particular, the claim only recites the additional elements of buffers and memory. These additional elements are recited at a high-level of generality and amount to no more than mere instructions to apply the exception using generic computer components (buffers and memory). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea (See MPEP 2106.05(f)). Step 2B Regarding the “ of one or more buffers to be stored in a shared memory ” limitation, such limitation is recited at a high-level of generality and amounts to no more than adding the words “apply it” (or an equivalent) with the judicial exception, because the limitation merely provides instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. Accordingly, this additional element does not add significantly more than the judicial exception. (See MPEP 2106.05(f)). Regarding Claim 8 Step 2A, Prong 1 Claim 8 recites a system that corresponds to the processor of claim 1, and therefore the analysis under Step 2A, Prong 1 with respect to claim 1 also applies to this claim 8. While claim 8 recites additional generic computing components (“processor”, “neural networks”), such additional generic computing components do not change the analysis under Step 2A, Prong 1. Step 2A, Prong 2 Claim 8 recites a system that corresponds to the processor of claim 1, and therefore the analysis under Step 2A, Prong 2 with respect to claim 1 also applies to this claim 8. While claim 8 recites additional generic computing components (“processor”, “neural networks”), such additional generic computing components do not change the analysis under Step 2A, Prong 2. Step 2B Claim 8 recites a system that corresponds to the processor of claim 1, and therefore the analysis under Step 2B with respect to claim 1 also applies to this claim 8. While claim 8 recites additional generic computing components (“processor”, “neural networks”), such additional generic computing components do not change the analysis under Step 2B. Claims 9-14 depend from claim 18 and recite systems that correspond to the processors of claims 2-7, respectively, and are therefore rejected for the same reasons explained above with respect to claim 8 and claims 2-7, respectively. Regarding Claim 15 Step 2A, Prong 1 Claim 15 recites a method that corresponds to the processor of claim 1, and therefore the analysis under Step 2A, Prong 1 with respect to claim 1 also applies to this claim 15. While claim 15 recites additional generic computing components (“neural networks”), such additional generic computing components do not change the analysis under Step 2A, Prong 1. Step 2A, Prong 2 Claim 15 recites a method that corresponds to the processor of claim 1, and therefore the analysis under Step 2A, Prong 2 with respect to claim 1 also applies to this claim 15. While claim 15 recites additional generic computing components (“neural networks”), such additional generic computing components do not change the analysis under Step 2A, Prong 2. Step 2B Claim 15 recites a method that corresponds to the processor of claim 1, and therefore the analysis under Step 2B with respect to claim 1 also applies to this claim 15. While claim 15 recites additional generic computing components (“neural networks”), such additional generic computing components do not change the analysis under Step 2B. Claims 16-20 depend from claim 15 and recite methods that correspond to the processors of claims 2-6, respectively, and are therefore rejected for the same reasons explained above with respect to claim 15 and claims 2-6, respectively. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 8, and 15 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by US 20220398747 A1, hereinafter referenced as LIN . Regarding Claim 1 LIN teaches: A processor, comprising: (LIN, para. 0005: “In another example, an apparatus for optical flow estimation of one or more frames is provided that includes a memory configured to store data corresponding to one or more frames and one or more processors (e.g., implemented in circuitry) coupled to the memory.”) one or more circuits to cause one or more neural networks to identify one or more first portions of first information to be used by the one or more neural networks to generate second information, (LIN, para. 0005: “In another example, an apparatus for optical flow estimation of one or more frames is provided that includes a memory configured to store data corresponding to one or more frames and one or more processors (e.g., implemented in circuitry) coupled to the memory.”; LIN, para. 0066: “As described above, the flow search area can be sized according to characteristics of the dataset being analyzed by the optical flow estimation system . ... The size of the flow search area selected by search area engine 104 can determine the computational and memory requirements for performing optical flow estimation. Accordingly, the search area engine 104 can also determine the size of the flow search are based at least in part on the available computing and memory resources (e.g., the amount of TCM) and the processing speed requirements for the optical flow estimation (e.g., whether the optical flow estimation needs to occur in real-time). In some cases, a neural network based machine learning system and/or algorithm (e.g., a deep neural network ) can be used to determine the size of the flow search area.”; Examiner’s Note: LIN discloses using a deep neural network, that takes the “available computing and memory resources” (corresponding to the recited “first portions of first information”) and outputs a size of a flow search (corresponding to recited “second information”), where the neural network needs to select or identify the correct type of input information) wherein the one or more neural networks are to identify the one or more first portions based, at least in part, on an amount of available storage. (LIN, para. 0044: “ In order to perform optical flow estimation quickly, such as in real-time optical flow estimation, a correlation volume can be stored in low-latency memory of a computing system (e.g., computing system 1100 described below). The lowest latency memory in a computing system, sometimes referred to as tightly coupled memory (TCM), may be limited in size. For example, TCM may be included on the same silicon die or within the same package as the processor of the computing system, limiting the available size available for the TCM. In some cases, when the size of the correlation volume exceeds the size of the TCM, some or all of the correlation volume can be stored in slower memory, such as memory accessible to the processor by direct memory access (DMA). Accordingly, techniques are needed that can reduce the required size of the correlation volume, which can enable faster optical flow estimation in systems that have limited available TCM.” LIN, para. 0066: “As described above, the flow search area can be sized according to characteristics of the dataset being analyzed by the optical flow estimation system . ... The size of the flow search area selected by search area engine 104 can determine the computational and memory requirements for performing optical flow estimation. Accordingly, the search area engine 104 can also determine the size of the flow search are based at least in part on the available computing and memory resources (e.g., the amount of TCM) and the processing speed requirements for the optical flow estimation (e.g., whether the optical flow estimation needs to occur in real-time). In some cases, a neural network based machine learning system and/or algorithm (e.g., a deep neural network ) can be used to determine the size of the flow search area.”; Examiner’s Note: the first portions (available memory) are selected from the larger group of available computing resources and memory, based on the neural network needing the available memory to make a prediction) Regarding Claim 8 LIN teaches: A system comprising: one or more processors to cause (LIN, para. 0050: “The components of the optical flow estimation system 100 can include electronic circuits or other electronic hardware, which can include one or more programmable electronic circuits (e.g., microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), central processing units (CPUs), or other suitable electronic circuits ), computer software, firmware, or any combination thereof, to perform the various operations described herein.”) The remaining limitations correspond to the processor of claim 1, and are therefore rejected for the same reasons explained above with respect to claim 1. Claim 15 recites a method that corresponds to the processor of claim 1, and is therefore rejected for the same reasons explained above with respect to claim 1 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over LIN in view of US 20250065916 A1, hereinafter referenced as GUPTA . Regarding Claim 2 LIN teaches the processor of claim 1 as explained above. However, LIN fails to explicitly teach: wherein the second information includes an expected relevance between the one or more first portions and one or more second portions. However, in a related field of endeavor (neural networks used with respect to image data, see para. 0027), GUPTA teaches and makes obvious: wherein the second information includes an expected relevance between the one or more first portions and one or more second portions. (GUPTA, para. 0036: “The trajectory model 212 may include a recurrent neural network (RNN) operably encoding the sequential kinematic data and output spatiotemporal output data, which include, without limitations, the kinematic data, road and lane data, and their relevance. ... By doing so, the input data and their relevance may be obtained and compressed to be output as the output data , such as spatiotemporal output data. The output data may include all the information in the input data and the relevance between the input data .”; Examiner’s Note: the LIN-GUPTA combination now modifies the neural network of LIN to additionally output the relevance (as in GUPTA) of the available memory (corresponding to recited “first portions”) with respect to the available computing resources (corresponding to recited “second portions”)) Before the effective filing date, it would have been obvious to one of ordinary skill in the art to combine the teachings of LIN with GUPTA as explained above. As disclosed by GUPTA, one of ordinary skill would have been motivated so that “each layer learns the relevance of input data and selects input data based on the relevance to pass to the next layer such that the next layer retains the data of input data are more relevant” and therefore the network utilizes higher relevancy data when making a prediction. (para. 0036). Claim 9 depends from claim 8 and recites a system that corresponds to the processor of claim 2, and is therefore rejected for the same reasons explained with respect to claims 2 and 8. Claim 16 depends from claim 15 and recites a method that corresponds to the processor of claim 2, and is therefore rejected for the same reasons explained with respect to claims 2 and 15 . 07-21-aia AIA Claim s 3-4, 6, 10-11, 13, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LIN in view of US 20220200669 A1, hereinafter referenced as GOWDA . Regarding Claim 3 LIN teaches the processor of claim 1 as explained above. However, LIN fails to explicitly teach: wherein the one or more neural networks are to identify the one or more first portions based, at least in part, on an amount of available storage of a graphics processing unit (GPU). However, in a related field of endeavor (neural networks, see para. 0092), GOWDA teaches and makes obvious: wherein the one or more neural networks are to identify the one or more first portions based, at least in part, on an amount of available storage of a graphics processing unit (GPU). (GOWDA, para. 0076: “In at least one embodiment, shared memory is shared memory available to a streaming multiprocessor (SM) of a GPU.”; Examiner’s Note: the LIN-GOWDA combination now selects the amount of memory capacity available (as in LIN) based on the memory capacity being from a GPU as taught by GOWDA) Before the effective filing date, it would have been obvious to one of ordinary skill in the art to combine the teachings of LIN with GOWDA as explained above. As disclosed by GOWDA, one of ordinary skill would have been motivated to utilize a GPU for parallel processing. (para. 0074). As further disclosed by GOWDA, one of ordinary skill would have been motivated to use a streaming multiprocessor of a GPU. (para. 0076). Regarding Claim 4 LIN teaches the processor of claim 1 as explained above. However, LIN fails to explicitly teach: wherein the one or more circuits are to use the one or more neural networks to perform one or more matrix multiplication operations using information of the one or more first portions. However, in a related field of endeavor (neural networks, see para. 0092), GOWDA teaches and makes obvious: wherein the one or more circuits are to use the one or more neural networks to perform one or more matrix multiplication operations using information of the one or more first portions. (GOWDA, para. 0075: “In at least one embodiment, precoding technique 400 includes generating precoding weights as values in a coefficient matrix W.sup.RZF=M.sup.H(D.sup.−1L.sup.−1), where D=diag(U). In at least one embodiment, augmented matrix 408 is referred to as a first augmented matrix, intermediate matrix 412 is referred to as a second augmented matrix, and generating precoding weights includes generating a conjugate transpose matrix M.sup.H of a first portion (e.g., matrix M) of second augmented matrix, and performing a matrix multiplication operation (e.g., multiplying M.sup.H by (D.sup.−1L.sup.−1)) based, at least in part, on generated conjugate transpose matrix M.sup.H.” GOWDA, para. 0429: “In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.”; Examiner’s Note: the LIN-GOWDA combination now performs neural network training using matrix multiplication as disclosed by GOWDA) Before the effective filing date, it would have been obvious to one of ordinary skill in the art to combine the teachings of LIN with GOWDA as explained above. As disclosed by GOWDA, one of ordinary skill would have been motivated to utilize a GPU for parallel processing. (para. 0074). As further disclosed by GOWDA, one of ordinary skill would have been motivated to do so in order to “accelerate machine learning application frameworks.” (para. 0276). Regarding Claim 6 LIN teaches the processor of claim 1 as explained above. However, LIN fails to explicitly teach: wherein the amount of available storage is based, at least in part, on one or more allocations to a GPU shared storage. However, in a related field of endeavor (neural networks, see para. 0092), GOWDA teaches and makes obvious: wherein the amount of available storage is based, at least in part, on one or more allocations to a GPU shared storage. (GOWDA, para. 0076: “In at least one embodiment, shared memory is shared memory available to a streaming multiprocessor (SM) of a GPU.”; Examiner’s Note: the LIN-GOWDA combination now selects the amount of memory capacity available (as in LIN) based on the memory capacity being from a GPU shared memory as taught by GOWDA) Before the effective filing date, it would have been obvious to one of ordinary skill in the art to combine the teachings of LIN with GOWDA as explained above. As disclosed by GOWDA, one of ordinary skill would have been motivated to utilize a GPU for parallel processing. (para. 0074). As further disclosed by GOWDA, one of ordinary skill would have been motivated to use a streaming multiprocessor of a GPU. (para. 0076). Claim 10 depends from claim 8 and recites a system that corresponds to the processor of claim 3, and is therefore rejected for the same reasons explained with respect to claims 3 and 8. Claim 11 depends from claim 8 and recites a system that corresponds to the processor of claim 4, and is therefore rejected for the same reasons explained with respect to claims 4 and 8. Claim 13 depends from claim 8 and recites a system that corresponds to the processor of claim 6, and is therefore rejected for the same reasons explained with respect to claims 6 and 8. Claim 17 depends from claim 15 and recites a method that corresponds to the processor of claim 3, and is therefore rejected for the same reasons explained with respect to claims 3 and 15. Claim 18 depends from claim 15 and recites a method that corresponds to the processor of claim 4, and is therefore rejected for the same reasons explained with respect to claims 4 and 15. Claim 20 depends from claim 15 and recites a method that corresponds to the processor of claim 6, and is therefore rejected for the same reasons explained with respect to claims 6 and 15 . 07-21-aia AIA Claim s 5, 12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over LIN in view of US 20060182357 A1, hereinafter referenced as LIU . Regarding Claim 5 LIN teaches the processor of claim 1 as explained above. However, LIN fails to explicitly teach: wherein the one or more first portions comprise are represented using a data format dynamically selected based, at least in part, on the amount of available storage. However, in a related field of endeavor (handling graphics and video content, see para. 0002), LIU teaches and makes obvious: wherein the one or more first portions comprise are represented using a data format dynamically selected based, at least in part, on the amount of available storage. (LIU, para. 0008: “The present invention, termed herein an Intelligent, dynamic, long-term digital Surveillance Media Storage System (ISMS), is a long-term digital media storage system with intelligent decision making based on event and content semantics to dynamically select the encoding method for new recording based on application defined priority and accuracy requirements. At the same time, it also, dynamically selects and converts previously recorded media to a less accurate recording format based on time and relative priority between a set of candidate media files and thus, forms a multistage media data compression mechanism that can best reduce the total storage size iteratively.”; LIU, para. 0024: “Thus, the system can dynamically and intelligently select a proper encoding mechanism to record or transcode the video to long-term surveillance media storages. As a result, this flexible profile architecture allows extending the system to fit any application needs.”; LIU, claim 3: “wherein said encoding optimizer processes media streams in multiple stages over time, each stage including dynamic selection of an encoding format based on an amount of available storage space ”; Examiner’s Note: the LIN-LIU combination now modifies LIN to select the available memory resources (as in LIN) to be formatted in a certain way based on the dynamic selection of an encoding format based on an amount of available storage space as in LIU) Before the effective filing date, it would have been obvious to one of ordinary skill in the art to combine the teachings of LIN with LIU as explained above. As disclosed by LIU, one of ordinary skill would have been motivated to select a particular encoding format in order to meet certain priorities, including at least available storage space. (para. 0008). As further disclosed by LIU, one of ordinary skill would have been motivated to do so in order to “reduce the storage demands.” (para. 0021). Claim 12 depends from claim 8 and recites a system that corresponds to the processor of claim 5, and is therefore rejected for the same reasons explained with respect to claims 5 and 8. Claim 19 depends from claim 15 and recites a method that corresponds to the processor of claim 5, and is therefore rejected for the same reasons explained with respect to claims 5 and 15 . 07-21-aia AIA Claims 7 and 14 are r ejected under 35 U.S.C. 103 as being unpatentable over L IN in view of US 20220301228 A1, hereinafter referenced as JUNKINS. H owever, in a related field of endeavor (graphics processing, see para. 0066), JUNKINS teaches and makes obvious: wherein the first information is represented using a tile data format of one or more buffers to be stored in a shared memory. (JUNKINS, para. 0270: “ Writing Native Tiling from Shared Local Memory Buffer —In some embodiments, an additional method refinement would allow compute shader kernels such as the Huffman decoder to directly write native tiled GPU format for block compressed textures.”; Examiner’s Note: The LIN-JUNKINS combination now modifies LIN to represent the available memory capacity as tiled GPU format as in JUNKINS). Before the effective filing date, it would have been obvious to one of ordinary skill in the art to combine the teachings of LIN with JUNKINS as explained above. As disclosed by JUNKINS, one of ordinary skill would have been motivated to do so in order to provide a “capability [that] would alleviate the GPU from having to run a secondary copy engine postprocessing pass to store the decoded texture in the native tiled GPU format.” (para. 0270). Claim 14 depends from claim 8 and recites a system that corresponds to the processor of claim 7, and is therefore rejected for the same reasons explained with respect to claims 7 and 8 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20240070812 A1 (Garrepalli). “Accordingly, the search area engine 104 may also determine the size of the flow search are based at least in part on the available computing and memory resources (e.g., the amount of TCM) and the processing speed requirements for the optical flow estimation (e.g., whether the optical flow estimation needs to occur in real-time). In some cases, a neural network-based machine learning system and/or algorithm (e.g., a deep neural network) may be used to determine the size of the flow search area.” (para. 0063). US 20230166604 A1 (Fu). “Hence, the relevance between the input data and the output data of the first ANN model 21 can be deduced. For the first ANN model 21, the activation function may be Softmax, the loss function may be Multi-Class Cross-Entropy Loss, the optimizer is Adam, and the learning rate is set to 0.001.” (para. 0028). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C LEE whose telephone number is (571)272-4933. The examiner can normally be reached M-F 12:00 pm - 8:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Omar Fernandez Rivas can be reached at 571-272-2589. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL C. 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