Prosecution Insights
Last updated: August 17, 2026
Application No. 18/440,207

DEVICE PACKAGES WITH PARTIALLY MOLDED CONNECTORS

Non-Final OA §103§112
Filed
Feb 13, 2024
Examiner
DAS, PINAKI
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
41 granted / 46 resolved
+21.1% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
37 currently pending
Career history
88
Total Applications
across all art units

Statute-Specific Performance

§103
48.0%
+8.0% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 46 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I and Claims 1-7 and 11-17 in the reply filed on 6/2/2026 is acknowledged. Claims 8-10 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/2/2026. Information Disclosure Statement Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered. Claim Objections Claims 12 and 14 are objected to because of the following informalities: Claim 12 recites the limitation, “bonding a connector body to a redistribution structure above a device die, -- redistribution structure including -- one or more redistribution layers” in lines 2-3. Examiner believes that it should recite, “bonding a connector body to a redistribution structure above a device die, -- the redistribution structure includes -- one or more redistribution layers”. Claim 14 recites the limitation, “comprising electrically coupling -- the connector body the device die -- via an electrical interconnect” in lines 1-2. Examiner believes that it should recite, “comprising electrically coupling -- the connector body and the device die -- via an electrical interconnect” Appropriate corrections are required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2, 5-6 and 11-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites the limitation wherein, “the connector body is an electrical connector configured to be coupled to a coaxial electrical cable.” It is unclear how the electrical connector is configured to be coupled to a coaxial electrical cable, since the electrical connector can be electrically connected to any intermediate cables/devices/connections before being connected to a coaxial electrical cable, and they will still be electrically coupled. It is unclear what special configuration is required or excluded in the above limitation. Hence, the claim is indefinite and rejected. Claim 5 recites the limitation wherein, “the first RDL is characterized by a first elastic modulus and the second RDL is characterized by a second elastic modulus that is lower than the first elastic modulus.” It is unclear what the applicant means by “the first RDL is characterized by a first elastic modulus” and “the second RDL is characterized by a second elastic modulus”. A RDL or a redistribution layer consists of dielectric layers with metal layers embedded in them. Therefore, it is unclear if the applicant means the elastic modulus of the dielectric layer only or the combined elastic modulus of the dielectric and the metal lines within the RDL. Hence the claim is indefinite and rejected. Claim 6 recites “a lower portion of the connector body” in lines 1-2. A “lower portion of the connector body” is already defined in claim 1 from which claim 6 depends on. It is unclear if the applicant is referring to the same “lower portion of the connector body” as in claim 1 or redefining it. For examination purposes, the limitation will be treated as “the lower portion of the connector body”. Claim 11 recites the limitation wherein, “the connector body is a fiber optic connector body configured to be coupled to an optical fiber.” It is unclear how the connector body is configured to be coupled to an optical fiber, since the connector body can be electrically connected to any intermediate cables/devices/connections before being connected to an optical fiber, and they will still be electrically coupled. It is unclear what special configuration is required or excluded for the fiber optic connector body. Hence, the claim is indefinite and rejected. Claim 12 recites the limitation wherein, “the connector body is an electrical connector configured to be coupled to a coaxial electrical cable or a fiber optic connector configured to be coupled to an optical fiber.” It is unclear how the electrical connector is configured to be coupled to a coaxial electrical cable, since the electrical connector can be electrically connected to any intermediate cables/devices/connections before being connected to a coaxial electrical cable, and they will still be electrically coupled. Similarly, it is also unclear how the connector body is configured to be coupled to an optical fiber, since the connector body can be electrically connected to any intermediate cables/devices/connections before being connected to an optical fiber, and they will still be electrically coupled. Therefore, it is unclear what special configuration is required or excluded for the electrical connector or the fiber optic connector in the above limitation. Hence, the claim is indefinite and rejected. Claims 13-17 depend from claim 12 and inherit the same indefiniteness and hence rejected. Claim 15 recites the limitation wherein, “the first RDL is characterized by a first elastic modulus and the second RDL is characterized by a second elastic modulus that is lower than the first elastic modulus.” It is unclear what the applicant means by “the first RDL is characterized by a first elastic modulus” and “the second RDL is characterized by a second elastic modulus”. A RDL or a redistribution layer consists of dielectric layers with metal layers embedded in them. Therefore, it is unclear if the applicant means the elastic modulus of the dielectric layer only or the combined elastic modulus of the dielectric and the metal lines within the RDL. Hence the claim is indefinite and rejected. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2015/0048500 A1) and further in view of Liu et al. (US 2019/0103353 A1). Re Claim 1, Yu teaches an electronic device package (Fig. 9) comprising: a device die (110, Fig. 9 , paras [0023] – [0024]) having an upper surface and a lower surface (upper and lower surfaces of 110, see Fig. 9); a redistribution structure (107, Fig. 9, also see Fig. 7, where 107 is marked, para [0038]) disposed on the upper surface of the device die (upper surface of 110), the redistribution structure including one or more redistribution layers (RDLs) formed from electrically insulating material and having electrical interconnects routed within them (see Fig. 9, also see Examiner notes below); a connector body (108+109, Fig. 9, para [0041]) disposed above the device die (110) and bonded to the redistribution structure (107, see Fig. 9); and a volume of molding material (101+112, Fig. 9, also see Fig. 7, where 112 is marked; 101 and 112, both can be made of polyimide molding material, paras [0034] and [0039]) which encapsulates the device die (110, see Fig. 9) and the redistribution structure (107, see Fig. 9) and surrounds lower portion of the connector body (lower portion of 108+109, see Fig. 9) such that an upper portion of the connector body is exposed at a first surface of the device package (upper portion of 108+109 is exposed, see Fig. 9). Regarding the redistribution structure, Examiner notes that Yu discloses that the RDL structure (107, Fig. 9) is formed of metals lines (para [0038]) but does not explicitly state that they are embedded within the insulating layers of the RDL (the insulating layers are shown in Fig. 9, but not explicitly stated). Related art Liu shows that a redistribution structure (108, Fig. 1A, para [0020]) comprises of conductive metal lines (116A-C, Fig. 1A, para [0024]) and vias (120A-C, Fig. 1A, para [0027]) which are embedded in the insulating dielectric layers (118A-E, Fig. 1A, para [0038]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the redistribution structure of Yu comprises of interconnect metal lines which are embedded within insulating layers as shown by Liu, as the insulating layers help in isolating the conductive lines within the RDL structure and prevent any short circuit. Re Claim 2, Yu modified by Liu teaches the electronic device package of claim 1, wherein the connector body (108+109, Fig. 9) is an electrical connector configured to be coupled to a coaxial electrical cable (The connector 108+109 can be configured to be electrically coupled to any electrical cable via any intermediate electrical cables/devices/connections). Re Claim 3, Yu modified by Liu teaches the electronic device package of claim 1, wherein the redistribution structure comprises a first RDL (marked “1st RDL” in annotated Fig. 9 below) disposed on the upper surface of the device die (110) and a second RDL (marked “2nd RDL” in annotated Fig. 9 below) disposed between the first RDL (“1st RDL”) and the connector body (108+109). PNG media_image1.png 497 937 media_image1.png Greyscale Re Claim 4, Yu modified by Liu teaches the electronic device package of claim 3, wherein the connector body (108+109) is electrically coupled to the device die (110) via an electrical interconnect (marked “electrical interconnect” in annotated Fig. 9 above) that is exposed at the upper surface of the redistribution structure (upper surface of 107) and passes through the first RDL (“1st RDL”) and the second RDL (“2nd RDL”). Re Claim 5, Yu modified by Liu teaches the electronic device package of claim 3, but does not disclose that the first RDL is characterized by a first elastic modulus and the second RDL is characterized by a second elastic modulus that is lower than the first elastic modulus. However, Liu discloses a similar redistribution structure (108, Fig. 1A, para [0020]) between a device die (102A, Fig. 1A, para [0020]) and a connector body (122, Fig. 1A, para [0028]), where the dielectric layer of the RDL closest to the connector body (dielectric layer 118E, Fig. 1A, para [0042]) has a lower modulus (para [0042]) than the one further away from the connector body (dielectric layer 118A, Fig. 1A, para [0042]), which will help to mitigate stress applied by the conductive connectors 122 (para [0042]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the redistribution structure of Yu, such that the dielectric layer of the “2nd RDL” which is closer to the connector body 108+109 (see annotated Fig. 9 of Yu above) has a lower elastic modulus than the dielectric layer of the “1st RDL” which is further away from the connector body. As disclosed by Liu (para [0042], Liu), this will help mitigate the stress applied by the connector body. Re Claim 6, Yu modified by Liu teaches the electronic device package of claim 1, wherein the lower portion of the connector body (lower portion of 108+109) is encapsulated within the volume of molding material (101+112, see Fig. 9). Re Claim 11, Yu modified by Liu teaches the electronic device package of claim 1, wherein the connector body (108+109, Fig. 9) is a fiber optic connector body configured to be coupled to an optical fiber (The connector 108+109 can be configured to be electrically coupled to an optical fiber, through any intermediate electrical connections). Re Claim 12, Yu teaches a method comprising: bonding a connector body (108+109, Fig. 9, para [0041]) to a redistribution structure (107, Fig. 9, also see Fig. 7, where 107 is marked, para [0038]) above a device die (110, Fig. 9 , paras [0023] – [0024]), the redistribution structure includes one or more redistribution layers (RDLs) formed from electrically insulating material and having electrical interconnects routed within them (see Fig. 9, also see Examiner notes below); and encapsulating the device die (110) and the redistribution structure (107) within a volume of molding material (101+112, Fig. 9, also see Fig. 7, where 112 is marked; 101 and 112, both can be made of polyimide molding material, paras [0034] and [0039]) such that a lower portion of the connector body (lower portion of 108+109) is surrounded by the volume of molding material (see Fig. 9) and an upper portion of the connector body (upper portion of 108+109) is exposed at a surface of a device package (see Fig. 9); wherein the connector body is an electrical connector configured to be coupled to a coaxial electrical cable (The connector 108+109 can be configured to be electrically coupled to any electrical cable via any intermediate electrical cables/devices/connections) or a fiber optic connector configured to be coupled to an optical fiber. Regarding the redistribution structure, Examiner notes that Yu discloses that the RDL structure (107, Fig. 9) is formed of metals lines (para [0038]) but does not explicitly state that they are embedded within the insulating layers of the RDL (the insulating layers are shown in Fig. 9, but not explicitly stated). Related art Liu shows that a redistribution structure (108, Fig. 1A, para [0020]) comprises of conductive metal lines (116A-C, Fig. 1A, para [0024]) and vias (120A-C, Fig. 1A, para [0027]) which are embedded in the insulating dielectric layers (118A-E, Fig. 1A, para [0038]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the redistribution structure of Yu comprises of interconnect metal lines which are embedded within insulating layers as shown by Liu, as the insulating layers help in isolating the conductive lines within the RDL structure and prevent any short circuit. Re Claim 13, Yu modified by Liu teaches the method of claim 12, wherein the redistribution structure comprises a first RDL (marked “1st RDL” in annotated Fig. 9 above) disposed on an upper surface of the device die (110) and a second RDL (marked “2nd RDL” in annotated Fig. 9 above) disposed between the first RDL (“1st RDL”) and the connector body (108+109). Re Claim 14, Yu modified by Liu teaches the method of claim 13, further comprising electrically coupling the connector body (108+109) and the device die (110) via an electrical interconnect (marked “electrical interconnect” in annotated Fig. 9 above) that is exposed at an upper surface of the redistribution structure (upper surface of 107) and passes through the first RDL (“1st RDL”) and the second RDL (“2nd RDL”). Re Claim 15, Yu modified by Liu teaches the method of claim 13, but does not disclose that the first RDL is characterized by a first elastic modulus and the second RDL is characterized by a second elastic modulus that is lower than the first elastic modulus. However, Liu discloses a similar redistribution structure (108, Fig. 1A, para [0020]) between a device die (102A, Fig. 1A, para [0020]) and a connector body (122, Fig. 1A, para [0028]), where the dielectric layer of the RDL closest to the connector body (dielectric layer 118E, Fig. 1A, para [0042]) has a lower modulus (para [0042]) than the one further away from the connector body (dielectric layer 118A, Fig. 1A, para [0042]), which will help to mitigate stress applied by the conductive connectors 122 (para [0042]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the redistribution structure of Yu, such that the dielectric layer of the “2nd RDL” which is closer to the connector body 108+109 (see annotated Fig. 9 of Yu above) has a lower elastic modulus than the dielectric layer of the “1st RDL” which is further away from the connector body. As disclosed by Liu (para [0042], Liu), this will help mitigate the stress applied by the connector body. Re Claim 16, Yu modified by Liu teaches the method of claim 12, further comprising encapsulating the lower portion of the connector body (lower portion of 108+109) within the volume of molding material (101+112, see Fig. 9). Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2015/0048500 A1) and Liu et al. (US 2019/0103353 A1), further in view of Lin et al. (US 2015/0255432 A1). Re Claim 7, Yu modified by Liu teaches the electronic device package of claim 1, wherein: the connector body (108+109, Fig. 9 of Yu) is electrically coupled to one or more electrical interconnects within the redistribution structure (electrical interconnects within RDL 107, see Fig. 9 of Yu). However, Yu modified by Liu does not disclose a carrier substrate and hence does not teach the following: further comprising a carrier substrate having a lower surface and an upper surface opposite the upper surface; wherein the lower surface of the device die is bonded to the upper surface of the carrier substrate; wherein the lower surface of the carrier substrate includes a set of external electrical contacts that are exposed at a second surface of the device package; and wherein the connector body is electrically coupled to one or more of the external electrical contacts via an electrical interconnect that passes through the carrier substrate. Related art Lin discloses a package substrate (202, Fig. 6, para [0024]) that is bonded to the device dies (204, Fig. 6, para [0024]), where the package substrate not only provides electrical connection to the device dies but also provides mechanical support, which ensures secure mounting and reduces the risk of damage from mechanical stress. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to attach a package substrate to the device of Yu as shown by Lin, as it not only provides electrical connection to the device dies but also provides mechanical support to the device dies, which ensures secure mounting and reduces the risk of damage from mechanical stress. Thus, Yu modified by Liu and Lin discloses: a carrier substrate (202, Fig. 6, para [0024], Lin) having a lower surface and an upper surface opposite the upper surface (upper and lower surfaces of 202); wherein the lower surface of the device die (lower surface of 110, Fig. 9 of Yu, similar to lower surface of die 204, Fig. 6 of Lin) is bonded to the upper surface of the carrier substrate (upper surface of 202, Lin); wherein the lower surface of the carrier substrate (lower surface of 202, Fig. 6 of Lin) includes a set of external electrical contacts (238, Fig. 6 of Lin) that are exposed at a second surface of the device package (see Fig. 6 of Lin); and wherein the connector body (108+109, Fig. 9 of Yu) is electrically coupled (device die 110 of Yu and package substrate 202 of Lin are electrically connected, see above) to one or more of the external electrical contacts (238, Fig. 6 of Lin) via an electrical interconnect that passes through the carrier substrate (electrical interconnect within 202, see Fig. 6 of Lin). Re Claim 17, Yu modified by Liu teaches the method of claim 12, wherein: the electrical connector (108+109, Fig. 9 of Yu) is electrically coupled to one or more electrical interconnects within the redistribution structure (electrical interconnects within RDL 107, see Fig. 9 of Yu) However, Yu modified by Liu does not disclose a carrier substrate and hence does not teach the following: further comprises a carrier substrate having a lower surface and an upper surface opposite the upper surface; wherein the lower surface of the device die is bonded to the upper surface of the carrier substrate; wherein the lower surface of the carrier substrate includes a set of external electrical contacts that are exposed at a second surface of the device package; and wherein the electrical connector is electrically coupled to one or more of the external electrical contacts via an electrical interconnect that passes through the carrier substrate. Related art Lin discloses a package substrate (202, Fig. 6, para [0024]) that is bonded to the device dies (204, Fig. 6, para [0024]), where the package substrate not only provides electrical connection to the device dies but also provides mechanical support, which ensures secure mounting and reduces the risk of damage from mechanical stress. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to attach a package substrate to the device of Yu as shown by Lin, as it not only provides electrical connection to the device dies but also provides mechanical support to the device dies, which ensures secure mounting and reduces the risk of damage from mechanical stress. Thus, Yu modified by Liu and Lin discloses: a carrier substrate (202, Fig. 6, para [0024], Lin) having a lower surface and an upper surface opposite the upper surface (upper and lower surfaces of 202); wherein the lower surface of the device die (lower surface of 110, Fig. 9 of Yu, similar to lower surface of die 204, Fig. 6 of Lin) is bonded to the upper surface of the carrier substrate (upper surface of 202, Lin); wherein the lower surface of the carrier substrate (lower surface of 202, Fig. 6 of Lin) includes a set of external electrical contacts (238, Fig. 6 of Lin) that are exposed at a second surface of the device package (see Fig. 6 of Lin); and wherein the electrical connector (108+109, Fig. 9 of Yu) is electrically coupled (device die 110 of Yu and package substrate 202 of Lin are electrically connected, see above) to one or more of the external electrical contacts (238, Fig. 6 of Lin) via an electrical interconnect that passes through the carrier substrate (electrical interconnect within 202, see Fig. 6 of Lin ). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Feb 13, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.7%)
3y 6m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 46 resolved cases by this examiner. Grant probability derived from career allowance rate.

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