CTNF 18/440,215 CTNF 99174 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 ( or as subject to pre-AIA 35 U.S.C. 102 and 103 ) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention ( s ) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102 ( b )( 2 )( C ) for any potential 35 U.S.C. 102 ( a )( 2 ) prior art against the later invention. 07-21-aia AIA Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 2022/0199517) . Regarding claim 1, Dabral teaches A semiconductor package comprising: a first semiconductor chip [ fig. 3, die 104A, para 64 ] ; a second semiconductor chip [ fig. 3, die 104B, para 64 ] spaced apart from the first semiconductor chip ( fig. 3, 104A ) in a first direction [ horizontal direction ] ; and a connection die [ fig. 3, BEOL build-up structure 120, para 63-64; wherein build up structure functions as a high density intra-chip connection die ] on the first semiconductor chip ( fig. 3, 104A ) and the second semiconductor chip ( fig. 3, 104B ) , wherein the first semiconductor chip ( fig. 3, 104A ) comprises a first semiconductor substrate [ fig. 3, substrate 101, para 62 ] comprising a first surface [ annotated fig. 3 ] and a second surface [ annotated fig. 3 ] , wherein the first surface and the second surface are on opposite sides of the first semiconductor substrate [ annotated fig. 3 ] , and wherein the first surface is closer than the second surface to the connection die [ annotated fig. 3 ] , wherein the second semiconductor chip ( fig. 3, 104B ) comprises a second semiconductor substrate ( fig. 3, 101; wherein para 58-59 discloses dicing is through the die to die routing areas 130 thereby forming two distinct dies ] having a third surface [ annotated fig. 3 ] and a fourth surface [ annotated fig. 3 ] , wherein the third surface and the fourth surface are on opposite sides of the second semiconductor substrate [ annotated fig. 3 ] , and wherein the third surface is closer than the fourth surface to the connection die [ annotated fig 3 ] . Dabral fails to explicitly disclose in fig. 3 wherein a hybrid bonding is established between the connection die and the first semiconductor chip and between the connection die and the second semiconductor chip, However, Dabral teaches in fig. 13B wherein a hybrid bonding is established between the connection die ( fig. 13B, 120 ) and the first semiconductor chip [ annotated fig. 13B ] and between the connection die and the second semiconductor chip [ annotated fig. 13 ] [ para 83, “The wafers can then be ( e.g. hybrid ) bonded front-to-back, face-to-face, or back-to-back.” ] Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to utilize hybrid bonding to enable ultra-high connection density which reduces signal latency and improves reliability of the device. Dabral further teaches in fig. 13B wherein the first semiconductor chip and the second semiconductor chip further comprise a power distribution wiring layer [ annotated fig. 13B ] disposed on the second surface of the first semiconductor chip and the fourth surface of the second semiconductor substrate [ annotated fig. 13B ] . 07-21-aia AIA Claim (s) 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 2022/0199517) as applied to claim 1 and further in view of Qiu (CN 114582858A) . Regarding claim 2, Dabral teaches The semiconductor package of claim 1, wherein the power distribution wiring layer [ annotated fig. 13B ] comprises: a dielectric layer [ para 62, “The BEOL build-up structure 120 may be fabricated using conventional materials including . . .insulating interlayer dielectrics ( ILD ) such as oxides ( e.g. silicon oxide, carbon doped oxides, etc. ) , nitrides ( e.g. silicon nitride ) , low-k, materials, etc.” ] a plurality of first power distribution lines [ fig. 13B, lower metal layers M_low, para 63 ] in the dielectric layer; and a plurality of second power distribution lines [ fig. 13B, upper metal layers M_high, para 63 ] in the dielectric layer, wherein the dielectric layer is in contact with the first semiconductor substrate and the second semiconductor substrate. Dabral fails to explicitly disclose a plurality of first power distribution lines in the dielectric layer; and a plurality of second power distribution lines in the dielectric layer, wherein the dielectric layer is in contact with the first semiconductor substrate and the second semiconductor substrate. However Qiu teaches a plurality of first power distribution lines [ fig. 3, conductive lines 271 ] in the dielectric layer [ fig. 3, wherein dielectric layers 270, 370, and insulating layer 250 are of the same material and considered one layer, “the first dielectric layer 270 and the second dielectric layer 370 include dielectric materials, such as silicon oxide, silicon nitride, carbide Silicon, silicon oxynitride, etc.” wherein all suggested materials are insulative ] and a plurality of second power distribution lines [ fig. 3, metal wires 371 ] in the dielectric layer ( fig. 3, 270/370/250 ) , wherein the dielectric layer ( fig. 3, 270/370/250 ) is in contact with the first semiconductor substrate [ fig. 3, first substrate 210 ] and the second semiconductor substrate [ fig. 3, second substrate 310 ] . Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the semiconductor structure to comprise a plurality of power distribution lines in the dielectric layer between two semiconductor structures to serve as a high density low-impedance power delivery network to maintain stable voltage without excessive power loss. Regarding claim 3, Dabral/Qiu teaches The semiconductor package of claim 2, wherein the dielectric layer ( fig. 3, 270/370/250 ) comprises a non-organic dielectric material [ Qiu discloses silicon oxide as a material which is non-organic dielectric material “the first dielectric layer 270 and the second dielectric layer 370 include dielectric materials, such as silicon oxide, silicon nitride, carbide Silicon, silicon oxynitride, etc.” ] . Regarding claim 4, Dabral/Qiu teaches The semiconductor package of claim 3, wherein the non-organic dielectric material comprises silicon oxide ( SiO 2 ) [ Qiu discloses silicon oxide as a material which is non-organic dielectric material “the first dielectric layer 270 and the second dielectric layer 370 include dielectric materials, such as silicon oxide, silicon nitride, carbide Silicon, silicon oxynitride, etc.” ] . 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 2022/0199517) as applied to claim 1 and further in view of Song et al. (KR 20210072181A) & Kwon et al. (US 2016/0118326) . Regarding claim 5, Dabral teaches The semiconductor package of claim 1. Dabral fails to explicitly disclose wherein the first semiconductor chip further comprises: a first circuit layer disposed on the first surface of the first semiconductor substrate; a first signal wiring layer disposed on the first circuit layer; and a first through electrode that penetrates the first semiconductor substrate, and wherein the second semiconductor chip further comprises: a second circuit layer disposed on the third surface of the second semiconductor substrate; a second signal wiring layer disposed on the second circuit layer; and a second through electrode that penetrates the second semiconductor substrate. However Song teaches wherein the first semiconductor chip [ annotated fig. 17 ] further comprises: a first circuit layer [ fig. 17, integrated circuits 400 ] disposed on the first surface ( top surface ) of the first semiconductor substrate [ annotated fig. 17 ] ; a first signal wiring layer [ fig. 17, wiring layer 1020 in first chip ] disposed on the first circuit layer [ fig. 17, integrated circuit 410 in first chip annotated fig. 17 ] ; and wherein the second semiconductor chip [ annotated fig. 17 ] further comprises: a second circuit layer [ annotated fig. 17 ] disposed on the third surface ( top surface ) of the second semiconductor substrate [ annotated fig. 17 ] ; a second signal wiring layer [ fig. 17, wiring layer 1020 in second chip ] disposed on the second circuit layer [ fig. 17, integrated circuit 410 in first chip annotated fig. 17 ] ; and Dabral/Song fails to explicitly disclose a first through electrode that penetrates the first semiconductor substrate, a second through electrode that penetrates the second semiconductor substrate. However Kwon teaches a first through electrode [ fig. 24, through electrodes 215, para 60 ] that penetrates the first semiconductor substrate [ fig. 24, substrate 212, para 60 ] , a second through electrode [ fig. 25, through electrodes 215, para 60 ] that penetrates the second semiconductor substrate [ fig. 25, substrate 212, para 60 ] . Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for through electrodes to penetrate semiconductor substrates to enable 3D IC stacking and integration to improve density and performance while reducing power consumption . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 15-20 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 6-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 6, Dabral/Song/Kwon teaches The semiconductor package of claim 5. The prior art of record singularly and/or in combination fails to explicitly teach wherein the connection die comprises: a third semiconductor substrate; and a connection wiring layer disposed on the third semiconductor substrate, wherein the connection wiring layer is connected to the first signal wiring layer and the second signal wiring layer. Thereby claim 6 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 7, Dabral teaches The semiconductor package of claim 1. While Dabral teaches stacking of semiconductor chips. Dabral fails to explicitly disclose a third semiconductor chip disposed on the first semiconductor chip; and a fourth semiconductor chip disposed on the second semiconductor chip, wherein the third semiconductor chip and the fourth semiconductor chip are spaced apart in the first direction and are disposed on opposites sides of the connection die, However Kwon teaches a third semiconductor chip [ annotated fig. 24 ] disposed on the first semiconductor chip [ annotated fig. 24 ] ; and a fourth semiconductor chip [ annotated fig. 24 ] disposed on the second semiconductor chip [ annotated fig. 24 ] , wherein the third semiconductor chip [ annotated fig. 24 ] and the fourth semiconductor chip [ annotated fig. 24 ] are spaced apart in the first direction ( horizontal direction ) . The prior art of record fails to explicitly disclose and are disposed on opposites sides of the connection die, wherein a hybrid bonding is established between the third semiconductor chip and the first semiconductor chip, and wherein a hybrid bonding is established between the fourth semiconductor chip and the second semiconductor chip. Thereby claim 7 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8-14 contain allowable subject matter at least based upon their dependency on claim 7. Regarding claim 15, Dabral teaches A semiconductor package, comprising: a first semiconductor chip [ fig. 3, die 104A, para 64 ] and a second semiconductor chip [ fig. 3, die 104B, para 64 ] that are spaced apart from each other in a first direction [ horizontal direction ] ; and a connection die [ fig. 3, BEOL build-up structure 120, para 63-64; wherein build up structure functions as a high density intra-chip connection die ] disposed on the first semiconductor chip ( fig. 3, 104A ) and the second semiconductor chip ( fig. 3, 104B ) , wherein the first semiconductor chip ( fig. 3, 104A ) comprises: a first semiconductor substrate [ fig. 3, substrate 101, para 62 ] having a first surface [ annotated fig. 3 ] and a second surface [ annotated fig. 3 ] , wherein the first surface and the second surface are on opposites sides of the first semiconductor substrate [ annotated fig. 3 ] , and wherein the first surface is closer than the second surface to the connection die [ annotated fig. 3 ] ; and wherein the second semiconductor chip comprises: a second semiconductor substrate ( fig. 3, 101; wherein para 58-59 discloses dicing is through the die to die routing areas 130 thereby forming two distinct dies ] having a third surface [ annotated fig. 3 ] and a fourth surface [ annotated fig. 3 ] , wherein the third surface and the fourth surface are on opposite sides of the second semiconductor substrate [ annotated fig. 3 ] , and wherein the third surface is closer than the fourth surface to the connection die [ annotated fig 3 ] . Dabral fails to explicitly disclose in fig. 3 wherein the first semiconductor chip and the second semiconductor chip further comprise a power distribution wiring layer disposed on the second surface of the first semiconductor substrate and the fourth surface of the second semiconductor substrate. However Dabral teaches in fig. 13B wherein the first semiconductor chip and the second semiconductor chip further comprise a power distribution wiring layer [ annotated fig. 13B ] disposed on the second surface of the first semiconductor chip and the fourth surface of the second semiconductor substrate [ annotated fig. 13B ] . Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the first and second semiconductor chips to comprise a power distribution wiring layer to improve power delivery efficiency while reducing thermal issues. Dabral fails to explicitly disclose a first through via that penetrates the first semiconductor substrate from the second surface toward the first surface, ; and a second through via that penetrates the second semiconductor substrate from the fourth surface toward the third surface, However Kwon teaches a first through via [ fig. 24, through electrodes 215, para 60 ] that penetrates the first semiconductor substrate [ fig. 24, substrate 212, para 60 ] , from the second surface toward the first surface [ fig. 24 top and bottom surfaces of substrate 212 ] , a second through via [ fig. 25, through electrodes 215, para 60 ] that penetrates the second semiconductor substrate [ fig. 25, substrate 212, para 60 ] . from the fourth surface toward the third surface [ top and bottom surfaces of the substrate ] . Dabral/Kwon fails to explicitly disclose wherein the power distribution wiring layer comprises: a common dielectric layer in contact with the second surface of the first semiconductor substrate and the fourth surface of the second semiconductor substrate; a first power distribution line connected to the first through via; and a second power distribution line connected to the second through via. However Qiu teaches wherein the power distribution wiring layer comprises: a common dielectric layer [ fig. 3, wherein dielectric layers 270, 370, and insulating layer 250 are of the same material and considered one layer, “the first dielectric layer 270 and the second dielectric layer 370 include dielectric materials, such as silicon oxide, silicon nitride, carbide Silicon, silicon oxynitride, etc.” wherein all suggested materials are insulative ] in contact with the second surface of the first semiconductor substrate [ fig. 3, first substrate 210 ] and the fourth surface of the second semiconductor substrate [ fig. 3, second substrate 310 ] ; The prior art of record fails to singularly and/or in combination to explicitly disclose a first wiring layer disposed on the first surface a second wiring layer disposed on the third surface; a first power distribution line connected to the first through via; and a second power distribution line connected to the second through via. Thereby claim 15 contains allowable subject matter. Claims 16-19 contain allowable subject matter at least based upon their dependency on claim 15 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is ( 703 ) 756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request ( AIR ) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center ( EBC ) at 866-217-9197 ( toll-free ) . If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 ( IN USA OR CANADA ) or 571-272-1000. /FELIX B ANDREWS/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/440,215 Page 2 Art Unit: 2812 Application/Control Number: 18/440,215 Page 3 Art Unit: 2812 Application/Control Number: 18/440,215 Page 5 Art Unit: 2812 Application/Control Number: 18/440,215 Page 6 Art Unit: 2812 Application/Control Number: 18/440,215 Page 7 Art Unit: 2812 Application/Control Number: 18/440,215 Page 8 Art Unit: 2812 Application/Control Number: 18/440,215 Page 9 Art Unit: 2812 Application/Control Number: 18/440,215 Page 11 Art Unit: 2812 Application/Control Number: 18/440,215 Page 12 Art Unit: 2812 Application/Control Number: 18/440,215 Page 14 Art Unit: 2812 Application/Control Number: 18/440,215 Page 15 Art Unit: 2812 Application/Control Number: 18/440,215 Page 16 Art Unit: 2812 Application/Control Number: 18/440,215 Page 17 Art Unit: 2812 Application/Control Number: 18/440,215 Page 18 Art Unit: 2812 Application/Control Number: 18/440,215 Page 19 Art Unit: 2812 Application/Control Number: 18/440,215 Page 20 Art Unit: 2812 Application/Control Number: 18/440,215 Page 21 Art Unit: 2812 Application/Control Number: 18/440,215 Page 22 Art Unit: 2812
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