DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Title Objection, filed 07/23/2026, with respect to the title have been fully considered and are persuasive. The objection of the title has been withdrawn.
Applicant’s arguments, see Rejections Under 35 U.S.C. § 103, filed 07/23/2026, with respect to the claims 1 & 6 have been fully considered and are persuasive.
Applicant’s arguments, see Rejections Under 35 U.S.C. § 103, filed 07/23/2026, with respect to the claim 12 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as detailed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chong (CN114497333A), Suh et al. (US 2017/0110629), & Kajiyama et al. (KR20200019133A).
Regarding claim 12, Chong teaches A method for manufacturing a micro light emitting diode (LED) panel, the method comprising:
laminating an conductive film [fig. 3c, bonding layer 160, “the material of the bonding layer 160 may be Au, Sn, In, Cu or Ti, etc.,”]on a panel substrate [fig. 3C, substrate 110, “the first substrate 110 may be a CMOS backplane or a TFT glass substrate, etc”];
forming a micro LED chip [fig. 3i, LED unit 100] comprising an electrode pad [fig. 3c, contacts 111, “each contact 111 drives one of the LED units 100”].
Chong fails to explicitly disclose an electrode pad comprising a groove structure that has a depth that increases from an edge of the electrode pad towards a center of the electrode pad in a stair form having at least two stairs
However Suh teaches an electrode pad [fig. 4B, electrode pad 261, para 74] comprising a groove structure that has a depth that increases from an edge of the electrode pad towards a center of the electrode pad in a stair form having at least two stairs [fig. 4B].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the electrode pad to comprise a groove wherein the depth of the groove increases towards a center to improve current spreading and reduced resistance thereby enhancing reliability of the device.
Chong/Suh fails to explicitly disclose transferring the micro LED chip onto the laminated panel substrate; and
thermally compressing the panel substrate onto which the micro LED chip is transferred.
However, Kajiyama (KR20200019133A) teaches transferring the micro LED chip [fig. 1-3, para 33] onto the laminated panel substrate [fig. 1-3, transfer substrate 5, para 33]; and
thermally compressing the panel substrate onto which the micro LED chip is transferred [para 18 & 50].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to transfer the micro LED chip onto a transfer substrate using thermal compression to enable high precision bonding of various LEDs on backplanes while ensuring reliable electrical connections.
Furthermore Kajiyama teaches laminating an anisotropic conductive film [fig. 12, anisotropic conductive film 7, para 42] on a panel substrate (fig. 12, transfer substrate 5).
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive film to be anisotropic to enable high density reliable bonding for MicroLEDs.
Regarding claim 13, Chong/Suh/Kajiyama teaches The method of claim 12,
wherein the forming the micro LED chip comprises:
sequentially forming a first semiconductor layer doped with an N-type dopant [Chong, fig. 3c, second doped type layer 150],
an active layer configured to emit light [Chong, fig. 3c, active layer 140, “the active layer (i.e., MQW layer) 140 is an active LED semiconductor layer, in the present embodiment, the semiconductor LED (first doped semiconductor layer type. The thickness of the active layer 140 and the second doped type layer 150)”], and
a second semiconductor layer doped with a P-type dopant [Chong, fig. 3c, first doped type layer 130, “the first doped type layer 130 may be a P-type semiconductor layer”] on a growth substrate [Chong, fig. 3c, substrate 110];
forming a pixel device [Chong, fig. 3i; LED units 100 excluding electrode layer 180] electrically spaced apart by etching the first semiconductor layer, the active layer, and the second semiconductor layer [Chong, fig. 3i; illustrates the forming of the pixel device (LED unit 100 excluding electrode layer 180) by etching of the first semiconductor layer (150), the second semiconductor layer (130), and the active layer (140); and
forming the electrode pad [Chong, fig. 3H, electrode layer 180] over the formed pixel device [Chong, fig. 3i; LED units 100 excluding electrode layer 180].
Claims 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chong (CN114497333A), Suh et al. (US 2017/0110629), & Kajiyama et al. (KR20200019133A) as applied to claims 12-13 and further in view of Lee et al. (US 2022/0336425).
Regarding claim 14, Chong/Suh/Kajiyama teaches The method of claim 12,
wherein the forming the micro LED chip comprises:
forming a first electrode pad [Chong, annotated fig. 3C] provided at a first region of a lower surface of the second semiconductor layer [Chong, annotated fig. 3C] and
a second electrode pad [Chong, annotated fig. 3C] provided at a second region of the second semiconductor layer [Chong, annotated fig. 3C] and
spaced apart from the first electrode pad by a distance [Chong, annotated fig. 3C].
Chong/Suh/Kajiyama fails to explicitly disclose a second electrode pad spaced apart from the first electrode pad by a distance that is less than or equal to 20 μm.
However Lee teaches a second electrode pad spaced apart from the first electrode pad by a distance that is less than or equal to 20 μm [fig. 3A, para 30, “the electrode pads are spaced apart from each other by about 3-300 μm. For example, in FIG. 3A, a distance DIS between the electrode pad N(n−1) of the P-N diode structure D(n−1) and the electrode pad Nn of the P-N diode structure Dn is about 3-300 μm.”].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the electrode pads to be spaced apart from each other by 3 -300 μm to optimize performance by enabling precise selective control over individual pixels and reducing electrical interference. Moreover, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. (MPEP 2144.05)
Allowable Subject Matter
Claims 1-2 & 4-11 allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, Chong (CN114497333A) teaches A micro light emitting diode (LED) chip comprising:
a first semiconductor layer doped with an N-type dopant [fig. 3c, second doped type layer 150];
a second semiconductor layer provided at a lower surface of the first semiconductor layer, and doped with a P-type dopant [fig. 3c, first doped type layer 130, “the first doped type layer 130 may be a P-type semiconductor layer”];
an active layer provided between the first semiconductor layer and the second semiconductor layer, and configured to emit light [fig. 3c, active layer 140, “the active layer (i.e., MQW layer) 140 is an active LED semiconductor layer, in the present embodiment, the semiconductor LED (first doped semiconductor layer type. The thickness of the active layer 140 and the second doped type layer 150)”]; and
an electrode pad [fig. 3c, contacts 111, “each contact 111 drives one of the LED units 100”] provided at a lower surface of the second semiconductor layer (fig. 3c, 130),
Chong fails to explicitly disclose wherein the electrode pad comprises a groove structure having a depth that increases from an edge of the electrode pad towards a center of the electrode pad.
However, Ye (WO2023122963A1) teaches wherein an electrode pad [fig. 3, bonding pad 13, “the bonding pad 13 is formed by, for example, a first metal layer 401 and a second metal layer 402 , so that the bonding pad 13 is provided with a groove 131 .”] comprises a groove structure (fig. 3, groove 131) having a depth that increases from an edge of the electrode pad towards a center of the electrode pad [fig. 3; wherein the depth of the groove 131 increases towards a center of the bonding pad 13].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the electrode pad to comprise a groove wherein the depth of the groove increases towards a center to improve current spreading and reduced resistance thereby enhancing reliability of the device.
The prior art of record fails to explicitly disclose wherein the electrode pad comprises a groove structure having a depth that continuously increases from an outer edge of the electrode pad towards a center of the electrode pad.
Thereby claim 1 contains allowable subject matter in light of the additional limitations recited therein.
Claims 2 & 4-5 contain allowable subject matter at least based upon their dependency on claim 1.
Regarding claim 6, Chong teaches A method for manufacturing a micro light emitting diode (LED) chip, the method comprising:
sequentially forming a first semiconductor layer doped with an N-type dopant [fig. 3c, second doped type layer 150],
an active layer configured to emit light [fig. 3c, active layer 140, “the active layer (i.e., MQW layer) 140 is an active LED semiconductor layer, in the present embodiment, the semiconductor LED (first doped semiconductor layer type. The thickness of the active layer 140 and the second doped type layer 150)”], and
a second semiconductor layer doped with a P-type dopant [fig. 3c, first doped type layer 130, “the first doped type layer 130 may be a P-type semiconductor layer”] on a growth substrate [fig. 3c, substrate 110, “The Micro-LED micro-display chip includes a first substrate 110”];
forming a pixel device [fig. 3i; LED units 100 excluding electrode layer 180] electrically spaced apart by etching the first semiconductor layer, the active layer, and the second semiconductor layer [fig. 3i; illustrates the forming of the pixel device (LED unit 100 excluding electrode layer 180) by etching of the first semiconductor layer (150), the second semiconductor layer (130), and the active layer (140); and
forming an electrode pad [fig. 3H, electrode layer 180] over the pixel device [fig. 3H, LED units 100 excluding electrode layer 180],
Chong fails to explicitly disclose wherein the electrode pad comprises a groove structure having a depth that increases from an edge of the electrode pad towards a center of the electrode pad.
However, Ye teaches wherein an electrode pad [fig. 3, bonding pad 13, “the bonding pad 13 is formed by, for example, a first metal layer 401 and a second metal layer 402 , so that the bonding pad 13 is provided with a groove 131 .”] comprises a groove structure (fig. 3, groove 131) having a depth that increases from an edge of the electrode pad towards a center of the electrode pad [fig. 3; wherein the depth of the groove 131 increases towards a center of the bonding pad 13].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the electrode pad to comprise a groove wherein the depth of the groove increases towards a center to improve current spreading and reduced resistance thereby enhancing reliability of the device.
The prior art of record fails to explicitly disclose wherein the electrode pad comprises a groove structure having a depth that continuously increases from an outer edge of the electrode pad towards a center of the electrode pad.
Thereby claim 6 contains allowable subject matter in light of the additional limitations recited therein.
Claim 7 -11 contain allowable subject matter at least based upon their dependency on claim 6.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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