DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II., there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/30/2026.
Applicant’s election without traverse of Invention I, claims 1-12 in the reply filed on 06/30/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "first region" in the 4th/5th line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, Examiner interprets “the first region” as “the first drain region”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2002/0034854 A1, hereinafter Lu ‘854) in view of You et al. (US 2017/0263722 A1, hereinafter You ‘722) in view of the following arguments.
PNG
media_image1.png
578
730
media_image1.png
Greyscale
With respect to Claim 1 Lu ‘854 discloses an electronic device (Fig 1-16) comprising:
a first transistor (600, Fig 6 and annotated Fig 11 of Lu ‘854, Para [0081], hereinafter FT) including a first drain region (leftmost 610 as shown in annotated Fig 11 of Lu ‘854, Para [0081], hereinafter 1DR) and a source region (center 515 as shown in annotated Fig 11 of Lu ‘854, Para [0081], hereinafter SR); and
a second transistor (600, Fig 6 and annotated Fig 11 of Lu ‘854, Para [0081], hereinafter ST) including (annotated Fig 11 of Lu ‘854 discloses ST included SR) the source region (SR) and a second drain region (rightmost 610 as shown in annotated Fig 11 of Lu ‘854, Para [0081], hereinafter 2DR),
But Lu ‘854 fails to expressly disclose the source region having a source junction depth shallower than a first drain junction depth of the first region (Note Examiner’s interpretation of “the first region” as “the first drain region”) and shallower than a second drain junction depth of the second drain region.
Nevertheless, in a related endeavor (Fig 1-6 of You ‘722), You ‘722 teaches the source region (110b, Fig 4 of You ‘722, Para [0082]) having a source junction depth (H1, Fig 4 of You ‘722, Para [0072]) shallower than (Fig 4 and Para [0072] of You ‘722 disclose H1 less than H2) a first drain junction depth (H2 of 120a, Fig 4 of You ‘722, Para [0072]) of the first region (120a, Fig 4 of You ‘722, Para [0082]) (Note Examiner’s interpretation of “first region” as “first drain region”) and shallower than (Fig 4 and Para [0072] of You ‘722 disclose H1 less than H2) a second drain junction depth (H2 of 120b, Fig 4 of You ‘722, Para [0072]) of the second drain region (120b, Fig 4 of You ‘722, Para [0082]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate You ‘722’s teaching of the source region having a source junction depth shallower than a first drain junction depth of the first drain region and shallower than a second drain junction depth of the second drain region into Lu ‘854’s device. Lu ‘854 discloses an asymmetric memory cell with a common source and teaches an asymmetric width of the source/drain regions and Lu ‘854 is open to the depth of the source/drain regions. You ‘722 also teaches an asymmetric memory cell with a common source and teaches both an asymmetric width and an asymmetric depth of the source/drain regions. The ordinary artisan would have been motivated to modify Lu ‘854 in the manner set forth above, at least, because as You ‘722 teaches in Para [0005] the taught asymmetric memory cell arrangement enhances current control capability, suppresses short channel effect and allows easier scaling.
As incorporated, You ‘722’s teaching of a source junction depth (H1) and the first drain junction depth (H2 of 120a) and second drain junction depth (H2 of 120b), H1 being shallower than H2 as described above, would be used as the depth of source region (SR) and the depth of first drain region (1DR) and second drain region (2DR), respectively, of Lu ‘854.
With respect to Claim 2 Lu ‘854 as modified by You ‘722 discloses all limitations of the electronic device of claim 1,
but Lu ‘854 as modified by You ‘722 fails to expressly disclose wherein the first drain junction depth is at least twice the source junction depth. However, the examiner notes that the applicant’s disclosure (Specification, Para [0013]) teaches wherein the recited asymmetric source/drains have the advantage of controlling the device operating threshold voltages. Having this mind, Lu ‘854 teaches in Para [0010 and 0108] that the asymmetric source/drain regions can be created to impact device voltages. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation of having the first drain junction depth at least two the source junction depth through routine optimization, to obtain the well-known advantage of impacting device operating voltages. See MPEP§2144.05 (II)(A),(B).
With respect to Claim 3 Lu ‘854 as modified by You ‘722 discloses all limitations of the electronic device of claim 1, and Lu ‘854 discloses further wherein the electronic device includes a p-type substrate (710, Fig. 10, Para [0105]) in which the first drain region (1DR), the second drain region (2DR), and the source region (SR) are disposed (1DR, 2DR and SR disposed in 710 is disclosed in Fig 10 and Para [0080]), with the first drain region (1DR) being a n-type region (Fig 10 discloses 1DR as n-type), the second drain region (2DR) being a n-type region (Fig 10 discloses 2DR as n-type), and the source region (SR) being a n-type region (Fig 10 discloses SR as n-type).
With respect to Claim 4 Lu ‘854 as modified by You ‘722 discloses all limitations of the electronic device of claim 1, and You ‘722 further discloses wherein the first drain region (120a of You ‘722) is separated from a third drain region (third drain region in region to left of 120a, Fig 4 of You ‘722) of a third transistor (third transistor in region to left of 120a, Fig 4 of You ‘722) by a first isolation region (105-1, Fig 4 of You ‘722, Para [0042]) and the second drain region (120b of You ‘722) is separated from a fourth drain region (fourth drain region in region to right of 120b, Fig 4 of You ‘722) of a fourth transistor (fourth transistor in region to right of 120b, Fig 4 of You ‘722) by a second isolation region (105-2, Fig 4 of You ‘722, Para [0042])(Fig 4 of You ‘722 and Para [0029-0030] disclose a plurality of the fin-type/gate electrodes/dummy gate electrodes extending in x1 direction, therefore a third drain region of a third transistor is separated from the first drain region 120a by 105-1 and a fourth drain region of a fourth transistor is separated from the second drain region 120b by 105-2).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate You ‘722’s further teaching of the first drain region is separated from a third drain region of a third transistor by a first isolation region and the second drain region is separated from a fourth drain region of a fourth transistor by a second isolation region into Lu ‘854 as modified by You ‘722’s device. The ordinary artisan would have been motivated to modify Lu ‘854 as modified by You ‘722 in the manner set forth above, at least, because these dielectric isolation features provide protection against parasitic capacitance between neighboring transistor devices.
As incorporated, the first isolation region (105-1) of You ‘722 would be used between first transistor (FT) and third transistor (transistor to left of FT as shown in Fig 10 of Lu ‘854) and the second isolation region (105-2) of You ‘722 would be used between the second transistor (ST) and fourth transistor (transistor to right of ST, right of image as shown in Fig 10 of Lu ‘854)in the device of Lu ‘854 as modified by You ‘722.
With respect to Claim 5 and 6 Lu ‘854 as modified by You ‘722 discloses all limitations of the electronic device of claim 1, and Lu ‘854 discloses further wherein the first transistor (FT) has a first gate structure (505 of FT, Fig 11, Para [0080]) having a first height (height of 505 of FT disclosed in annotated Fig 11 of Lu ‘854) and the second transistor (ST) has a second gate structure (505 of ST, Fig 11, Para [0080]) having a second height (height of 505 of ST disclosed in annotated Fig 11 of Lu ‘854).
Lu ‘854 as modified by You ‘722 fails to explicitly disclose such that, in fabrication, the first gate structure and second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant and Lu ‘854 as modified by You ‘722 fails to explicitly disclose claim 6, “wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region”.
The language, term, or phrase "in fabrication, the first gate structure and second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant and wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region", is directed towards the process of making a doped source drain region. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how it is actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "in fabrication, the first gate structure and second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant and wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region" only requires the structure of claim 1 and “wherein the first transistor has a first gate structure having a first height and the second transistor has a second gate structure having a second height”, which does not distinguish the invention from Lu ‘854 as modified by You ‘722, who teaches the structure as claimed.
With respect to Claim 7 Lu ‘854 as modified by You ‘722 discloses all limitations of the electronic device of claim 1, and Lu ‘854 further discloses wherein the first transistor (FT) has a threshold voltage matched to a threshold voltage of the second transistor (ST)(Para [0010 and 0059] discloses memory cells of a particular set have a unique threshold voltage and Para [0038] discloses a cell share a common source, therefore FT and ST are a set and have the same threshold voltage).
With respect to Claim 8 Lu ‘854 discloses a system comprising:
a memory device (device of Fig 1-15) having a memory cell array (memory array of Fig 15 and Para [0128]) coupled to a sense amplifier (1510, Fig 15, Para [0129]), the sense amplifier (1510) having:
a first transistor (1540 of Fig 15 and Para [0130], shown as 600, Fig 6 and annotated Fig 11 of Lu ‘854, Para [0081], hereinafter FT) including a first drain region (leftmost 610 as shown in annotated Fig 11 of Lu ‘854, Para [0081], hereinafter 1DR) and a source region (center 515 as shown in annotated Fig 11 of Lu ‘854, Para [0081], hereinafter SR); and
a second transistor (1525 of Fig 15 and Para [0130], shown as 600, Fig 6 and annotated Fig 11 of Lu ‘854, Para [0081], hereinafter ST) including (annotated Fig 11 of Lu ‘854 discloses ST included SR) the source region (SR, Para [0130] discloses 1540 and 1525 share the source region) and a second drain region (rightmost 610 as shown in annotated Fig 11 of Lu ‘854, Para [0081], hereinafter 2DR),
But Lu ‘854 fails to expressly disclose the source region having a source junction depth shallower than a first drain junction depth of the first drain region and shallower than a second drain junction depth of the second drain region.
Nevertheless, in a related endeavor (Fig 1-6 of You ‘722), You ‘722 teaches the source region (110b, Fig 4 of You ‘722, Para [0082]) having a source junction depth (H1, Fig 4 of You ‘722, Para [0072]) shallower than (Fig 4 and Para [0072] of You ‘722 disclose H1 less than H2) a first drain junction depth (H2 of 120a, Fig 4 of You ‘722, Para [0072]) of the first drain region (120a, Fig 4 of You ‘722, Para [0082]) and shallower than (Fig 4 and Para [0072] of You ‘722 disclose H1 less than H2) a second drain junction depth (H2 of 120b, Fig 4 of You ‘722, Para [0072]) of the second drain region (120b, Fig 4 of You ‘722, Para [0082]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate You ‘722’s teaching of the source region having a source junction depth shallower than a first drain junction depth of the first drain region and shallower than a second drain junction depth of the second drain region into Lu ‘854’s device. Lu ‘854 discloses an asymmetric memory cell with a common source and teaches an asymmetric width of the source/drain regions and Lu ‘854 is open to the depth of the source/drain regions. You ‘722 also teaches an asymmetric memory cell with a common source and teaches both an asymmetric width and an asymmetric depth of the source/drain regions. The ordinary artisan would have been motivated to modify Lu ‘854 in the manner set forth above, at least, because as You ‘722 teaches in Para [0005] the taught asymmetric memory cell arrangement enhances current control capability, suppresses short channel effect and allows easier scaling.
As incorporated, You ‘722’s teaching of a source junction depth (H1) and the first drain junction depth (H2 of 120a) and second drain junction depth (H2 of 120b), H1 being shallower than H2 as described above, would be used as the depth of source region (SR) and the depth of first drain region (1DR) and second drain region (2DR), respectively, of Lu ‘854.
With respect to Claim 9 Lu ‘854 as modified by You ‘722 discloses all limitations of the electronic device of claim 8,
but Lu ‘854 as modified by You ‘722 fails to expressly disclose wherein the first drain junction depth is at least twice the source junction depth. However, the examiner notes that the applicant’s disclosure (Specification, Para [0013]) teaches wherein the recited asymmetric source/drains have the advantage of controlling the device operating threshold voltages. Having this mind, Lu ‘854 teaches in Para [0010 and 0108] that the asymmetric source/drain regions can be created to impact device voltages. Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation of having the first drain junction depth at least two the source junction depth through routine optimization, to obtain the well-known advantage of impacting device operating voltages. See MPEP§2144.05 (II)(A),(B).
With respect to Claims 10 and 11 Lu ‘854 as modified by You ‘722 discloses all limitations of the system of claim 8, and Lu ‘854 discloses further wherein the first transistor (FT) has a first gate structure (505 of FT, Fig 11, Para [0080]) having a first height (height of 505 of FT disclosed in annotated Fig 11 of Lu ‘854) and the second transistor (ST) has a second gate structure (505 of ST, Fig 11, Para [0080]) having a second height (height of 505 of ST disclosed in annotated Fig 11 of Lu ‘854)
Lu ‘854 as modified by You ‘722 fails to explicitly disclose such that, in fabrication, the first gate structure and second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant and Lu ‘854 as modified by You ‘722 fails to expressly disclose claim 11, “wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region”.
The language, term, or phrase "in fabrication, the first gate structure and second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant and wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region", is directed towards the process of making a doped source drain region. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how it is actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "in fabrication, the first gate structure and second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant and wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region" only requires the structure of claim 1 and “wherein the first transistor has a first gate structure having a first height and the second transistor has a second gate structure having a second height”, which does not distinguish the invention from Lu ‘854 as modified by You ‘722, who teaches the structure as claimed.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lu ‘854 in view of You ‘722 in further view of Park et al. (US 2009/0262587 A1, hereinafter Park ‘587), in view of the following arguments.
With respect to Claim 12 Lu ‘854 as modified by You ‘722 discloses all limitations of the system of claim 8, but Lu ‘854 as modified by You ‘722 fails to expressly disclose wherein the sense amplifier is a p-type sense amplifier.
Nevertheless, in a related endeavor (Fig 1-8 of Park ‘587), Park ‘587 teaches wherein the sense amplifier (PSA, Fig 7 of Park ‘587, Para [0095]) is a p-type sense amplifier (Para [0095] of Park ‘587 discloses PSA as a p-type sense amplifier).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘587’s teaching of wherein the sense amplifier is a p-type sense amplifier into Lu ‘854 as modified by You ‘722’s device. Lu ‘854 as modified by You ‘722 discloses a memory device, the cells with a common source connected to a sense amplifier. Park ‘587 also teaches a memory device, the cells with a common source connected to a sense amplifier and that the sense amplifier can be p-type of n-type. Park ‘587 teaches the operation of a sense amplifier connected to an NMOS or a PMOS depending on the desired on/off configuration of the device. The ordinary artisan would have been motivated to modify Lu ‘854 as modified by You ‘722 in the manner set forth above, at least, because it is immaterial if the on state is controlled by an on or off voltage. It would be obvious to one of ordinary skill in the art that it is a design choice to connect the sense amplifier to a PMOS, leading to a p-type sense amplifier which would control which bit lines were to be sensed.
As incorporated, the teaching of Park ‘587 of a p-type sense amplifier would be used in the device of Lu ‘854 as modified by You ‘722 such that sense amplifier (1510) of Lu ‘854 as modified by You ‘722 would be p-type.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights