Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-8 in the reply filed on 06/08/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim(US 20230054984 A1, hereafter Kim).
Regarding Claim 1, Kim discloses:
An electronic device(Fig. 1) comprising:
One or more electronic dies(Fig. 1 [300/400]);
A lower substrate(Fig. 1 [100]) on which the one or more electronic dies(Fig. 1 [300/400]) are positioned;
An upper substrate(Fig. 1 See figure below) above the lower substrate(Fig. 1 [100]), the upper substrate(Fig. 1 See figure below), the upper substrate(Fig. 1 See figure below) having an opening(Fig. 1 See figure below) above the one or more electronic dies(Fig. 1 [300/400]);
A downset substrate(Fig. 1 See figure below) connecting the upper substrate(Fig. 1 See figure below) to the lower substrate(Fig. 1 [100]), the downset substrate(Fig. 1 See figure below) having one or more vias(Fig. 1 See figure below) between the upper substrate(Fig. 1 See figure below) and the lower substrate(Fig. 1 [100]); and
A non-conductive film(Fig. 1 [500]) disposed in the opening of the upper substrate(Fig. 1 See figure below), on the one or more electronic dies(Fig. 1 [300/400]) and on sidewalls of the downset substrate(Fig. 1 See figure below).
While Kim does not explicitly call the chips(Fig. 1 [300/400]) as dies, a review of the specification provided by Kim as well as the specification of the application at hand would reveal to one of ordinary skill in the art that these are analogous structures. Firstly, Kim refers to the chips as possible a logic chip or a NAND flash memory(See paragraphs 0029-0031). This is analogous to the disclosure by the applicant of the dies as “NAND memory dies”(See paragraph 0018 of the specification of the application). In addition, the application at hand explicitly refers to the disclosed package as an “architecture for a conventional multichip package memory”. Based off of these respective disclosures, one of ordinary skill in the art would naturally arrive at the claim at hand with the disclosure provided by Kim, based off of their teachings and provided structure. This would produce a predictable result in the creation of the device disclosed by Kim.
Regarding Claim 2, Kim further discloses:
One or more additional electronic dies(Fig. 1 [700]) are positioned above and supported by the non-conductive film(Fig. 1 [500]).
Regarding Claim 3, Kim further discloses:
The electronic device(Fig. 1) is a packaged electronic device having a neutral axis at a top surface of the one or more additional electronic dies(Fig. 1 [700]).
Regarding Claim 4, Kim further discloses:
The electronic device(Fig. 1) includes package electrical contacts(Fig. 1 [130]) coupled to the lower substrate(Fig. 1 [100]), one or more of the package electrical contacts(Fig. 1 [130]) configured to provide signals(See paragraph 0046 “for eample, the second pads 623 and the third pads 624 may be connected through connection lines 626”), via the one or more vias(Fig. 1 See figure below) between the one or more additional electronic dies(Fig. 1 [700]) and one or more devices external to the electronic device(Fig. 1).
While Kim does not explicitly disclose these one or more devices, given Kim’s disclosure of the field of technology being the bonding of a chip to a printed circuit board(See paragraph 0004), one of ordinary skill in the art would understand the terminals labeled as external terminals(Fig. 1 [130]) would be utilized to connect the chips to external devices.
Regarding Claim 5, Kim further discloses:
The electronic device(Fig. 1) includes package electrical contacts(Fig. 1 [310]) coupled to the lower substrate(Fig. 1 [100]), one or more of the package electrical contacts(Fig. 1 [310]) configured to provide signals between the one or more electronic dies(Fig. 1 [300/400]) and one or more devices eternal to the electronic device(Fig. 1).
See the justification above regarding Kim’s not disclosing the devices external to the electronic device.
Regarding Claim 6, Kim further discloses:
The upper substrate(Fig. 1 See figure below) is a continuous structure around the opening(See paragraph 0026), the continuous structure(See paragraph 0026) including conductive paths(Fig. 1 See figure below) coupled to the one or more vias(Fig. 1 See figure below).
While Kim does not explicitly teach or disclose the continuous nature of the connection substrate(Fig. 1 [200]), one of ordinary skill in the art would recognize that creating an opening in the connection substrate would generate one of a limited number of choices in the shape of the remaining connection substrate, and in the context of providing a housing for a chip(Fig. 1 [300/400]), the most natural option would be to form the upper substrate in a continuous shape around the chips.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Huang(US 20220302022 A1, hereafter Huang).
Regarding Claim 7, Kim further discloses:
A first portion(Fig. 1 See figure below) and a second portion(Fig. 1 See figure below), the first portion(Fig. 1 See figure below) including a first set of conductive paths(Fig. 1 See figure below) coupled to a first via set of the one or more vias(Fig. 1 See figure below) and the second portion(Fig. 1 See figure below) including a second set of conductive paths(Fig. 1 See figure below) coupled to a second via set of the one or more vias(Fig. 1 See figure below).
Kim does not teach or disclose the opening of the upper substrate separates a first portion of the upper substrate from a second portion of the upper substrate such that the upper substrate is non-continuous between the first portion and the second portion.
In the same field of endeavor, Huang discloses:
The opening(Fig. 1 [310]) of the upper substrate(Fig. 1 [10a/10a2]) separates a first portion(Fig. 1 [10a]) of the upper substrate(Fig. 1 [10a/10a2]) from a second portion(Fig. 1 [10a2]) of the upper substrate(Fig. 1 [10a/10a2]) is non-continuous between the first portion(Fig. 1 [10a]) and the second portion(Fig. 1 [10a2]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Kim along the lines of Huang. One might have been motivated to form a discontinuous upper substrate in order to better match the coefficient of thermal expansion of the upper substrate against the nonconductive molding film, as is an element of the invention provided by Huang(See paragraph 0026 of Huang). Performing this modification would have generated a predictable result in the creation of Kim’s device with a discontinuous upper substrate as disclosed by Huang.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Joo et al.(US 20210265274 A1, hereafter Joo).
Regarding Claim 8,
Kim discloses one or more additional electronic dies(Fig. 1 [700]) positioned above and supported by the non-conductive film.
Kim does not teach or disclose a mold compound structured to provide a cover to the one or more additional electronic dies, the upper substrate, the downset substrate, and the lower substrate.
In the same field of endeavor, Joo discloses a mold compound(Fig. 1 [130]) providing cover to an additional electronic die(Fig. 1 [200]), an upper substrate(Fig. 1 [110b]), a downset substrate(Fig. 1 [110a]), and the lower substrate(Fig. 1 [140]).
It would have been obvious to modify the device disclosed by Kim along the lines of Joo. One might have been motivated to include Joo’s molding compound in order to protect and isolate the additional electronic die. Performing this modification would have generated a predictable result in Kim’s device with a molding compound atop the additional electronic die.
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Above: Fig. 1 of Kim with upper and downset substrates, vias, conductive paths, first and second portions, and opening denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chiu et al.(US 20230062468 A1) discloses a semiconductor package device. Yang(US 20240153833 A1) discloses a semiconductor package device. Park(US 20230343746 A1) discloses a multilayered stacked semiconductor package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
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