DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (Figs. 1-6) in the reply filed on 06/29/2026 is acknowledged.
Claims 1-18 read on the elected species and are examined in the action below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/13/2024 and 05/28/2026 are being considered by the examiner.
Drawings
The drawings submitted on 02/13/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kato et al. (US 20210280556 A1).
Regarding claim 1, Kato discloses a semiconductor device comprising:
two first semiconductor elements (3a/3c) each including a first electrode (drain), a second electrode (source), and a third electrode (30) and each controlled to switch between an on-state and an off-state by a first drive signal inputted to the third electrode (30); ([0039], Fig. 1)
a first conductor (conductive layer 23 annotated below) electrically interposed between the first electrodes (drains) of the two first semiconductor elements (3a/3c); ([0039], Fig. 1) and
a first power terminal (17) electrically connected to the first conductor (conductive layer 23 annotated below) and electrically conducting to the first electrodes (drains) of the two first semiconductor elements (3a/3c),
wherein the two first semiconductor elements (3a/3c) are electrically connected in parallel (per [0040]), and
the first conductor (conductive layer 23 annotated below) is disposed to avoid being located on a portion of a first line segment (annotated below) connecting centers of the two first semiconductor elements (3a/3c) as viewed in a thickness direction of the first conductor. (Fig. 1)
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al. (US 20210280556 A1).
Regarding claim 2, Kato discloses the semiconductor device according to claim 1. Kato does not explicitly disclose wherein the first conductor is disposed to avoid being located on at least 15% and at most 90% of the first line segment as viewed in the thickness direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the first conductor is disposed to avoid being located on at least 15% and at most 90% of the first line segment as viewed in the thickness direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 so as to “provide a semiconductor module that can reduce gate-source inductance and suppress fluctuations of the inductance.” (Kato, [0007])
Regarding claim 3, Kato discloses the semiconductor device according to claim 1, the first conductor (conductive layer 23 annotated above). (Fig. 1)
Kato does not explicitly disclose:
includes two first mounting portions on which the two first semiconductor elements are mounted,
the two first mounting portions are disposed with a first gap interposed therebetween in a first direction orthogonal to the thickness direction, and
the first gap intersects the first line segment as viewed in the thickness direction.
However, Kato shows in Fig. 1 and 2:
includes two first mounting portions (portions of 23a/23b under the semiconductor elements 3a/3c) on which the two first semiconductor elements (3a/3c) are mounted,
the two first mounting portions (portion of 23a/23b under the elements 3a/3c) are disposed with a first gap (see Fig. 1-2) interposed therebetween in a first direction (x-direction) orthogonal to the thickness direction (y-direction), and
the first gap intersects the first line segment (center of 3a to center of 3c) as viewed in the thickness direction. ([0040]-[0041], Fig. 1-2)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Kato for two first mounting portions on which the two first semiconductor elements are mounted, the two first mounting portions are disposed with a first gap interposed therebetween in a first direction orthogonal to the thickness direction, and the first gap intersects the first line segment as viewed in the thickness direction in order to “ not only the inductance between the PN terminals can be reduced, but also the gate-source inductance can be reduced, and fluctuations of the inductances can further be suppressed.” (Kato, [0073)
Regarding claim 4, Kato discloses the semiconductor device according to claim 3, wherein the first conductor(conductive layer 23 annotated above) includes a first connecting portion (23c) connected to both of the two first mounting portions (23a/23b), and
the first connecting portion (23c) is located in a first sense of a second direction orthogonal to the thickness direction and the first direction from the first line segment (from center of 3a to center of 3c). (Fig. 1 and 2)
Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al. (US 20210280556 A1) as applied to claim 4 above, and further in view of Hayashiguchi (US 20220254758 A1).
Regarding claim 5, Kato discloses the semiconductor device according to claim 4. Kato does not disclose wherein the first conductor includes a pad portion to which the first power terminal is bonded,
the first power terminal is located farther in a first sense of the first direction than the two first semiconductor elements, and
the first connecting portion extends from the pad portion in a second sense of the first direction as viewed in the thickness direction.
However, Hayashiguchi discloses:
the first conductor (226) includes a pad portion (226b) to which the first power terminal (36) is bonded, ([0092], Fig. 10)
the first power terminal (36) is located farther in a first sense of the first direction (x-direction) than the two first semiconductor elements (13), (Fig. 10) and
the first connecting portion (226a) extends from the pad portion (226a) in a second sense of the first direction (x-direction) as viewed in the thickness direction. ([0092], Fig. 13)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kato and Hayashiguchi for the first conductor includes a pad portion to which the first power terminal is bonded, the first power terminal is located farther in a first sense of the first direction than the two first semiconductor elements, and the first connecting portion extends from the pad portion in a second sense of the first direction as viewed in the thickness direction in order to “improve the short-circuit tolerance of the semiconductor element.” (Hayashiguchi, [0008])
Regarding claim 6, Hayashiguchi discloses the semiconductor device according to claim 5, wherein each of the two first semiconductor elements (13) includes a first-element obverse surface (13a) and a first-element reverse surface (13b) spaced apart in the thickness direction, ([0086], Fig. 10)
the first electrode (132) is disposed on the first-element reverse surface (13b), ([0086]-[0087], Fig. 10)
the second electrode (131) and the third electrode (133) are disposed on the first-element obverse surface (13a), (Fig. 12 and 13) and
each of the two first semiconductor elements (13) is disposed with the first-element reverse surface (13b) facing the first conductor (226). (Fig. 13)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Hayashiguchi to arrive at the claimed invention for similar reasons mentioned beforehand.
Regarding claim 7, Hayashiguchi discloses the semiconductor device according to claim 6, further comprising:
a second conductor (223) spaced apart from the first conductor (226); ([0047], Fig. 10)
two first connecting members (62) electrically connecting the second conductor (223) and the second electrode (131) of each of the two first semiconductor elements (13); ([0082], Fig. 12) and
a second power terminal (36) electrically connected to the second conductor (223) and electrically conducting to the second electrodes (131) of the two first semiconductor elements (13). ([0082], Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Hayashiguchi to arrive at the claimed invention for similar reasons mentioned beforehand.
Regarding claim 8, Hayashiguchi discloses the semiconductor device according to claim 7, wherein the second conductor (223) is located on a same side as the two first mounting portions (portion of 223 under 13) in the second direction (y-direction) with respect to the first connecting portion (226a). (Fig. 10 and 13)
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It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Hayashiguchi to arrive at the claimed invention for similar reasons mentioned beforehand.
Regarding claim 9, Hayashiguchi discloses the semiconductor device according to claim 8, wherein the second conductor (223) includes a projecting portion (223a annotated below) protruding in the second direction (y-direction) as viewed in the thickness direction and overlapping in part with the first gap as viewed in the thickness direction. (Fig. 13)
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It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Hayashiguchi to arrive at the claimed invention for similar reasons mentioned beforehand.
Regarding claim 10, Hayashiguchi discloses the semiconductor device according to claim 8, further comprising two second semiconductor elements (11) each including a fourth electrode (112), a fifth electrode (111), and a sixth electrode (113) and each controlled to switch between an on-state and an off-state by a second drive signal (per [0057]) inputted to the sixth electrode (113), (Fig. 10)
wherein the two second semiconductor elements (11) are electrically connected in parallel, ([0032], Fig. 10)
the second conductor (223) is electrically interposed between the fourth electrodes (112) of the two second semiconductor elements (111), (Fig. 10) and
the second power terminal (31) is electrically conducting to the fourth electrodes (112) of the two second semiconductor elements (111). (Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Hayashiguchi to arrive at the claimed invention for similar reasons mentioned beforehand.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashiguchi (US 20220254758 A1) as applied to claim 10 above, and further in view of Kato et al. (US 20210280556 A1).
Regarding claim 11, Hayashiguchi discloses the semiconductor device according to claim 10. Hayashiguchi does not disclose wherein the second conductor is disposed to avoid being located on a portion of a second line segment connecting centers of the two second semiconductor elements as viewed in the thickness direction.
However, Kato discloses:
the second conductor (annotated below) is disposed to avoid being located on a portion of a second line segment (annotated below) connecting centers of the two second semiconductor elements (3b/3d) as viewed in the thickness direction. (Fig. 2)
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hayashiguchi and Kato for the second conductor is disposed to avoid being located on a portion of a second line segment connecting centers of the two second semiconductor elements as viewed in the thickness direction so that “the inductance between the PN terminals can be reduced, but also the gate-source inductance can be reduced, and fluctuations of the inductances can further be suppressed.” (Kato, [0073])
Regarding claim 12, Kato discloses the semiconductor device according to claim 11. Kato does not explicitly disclose wherein the second conductor is disposed to avoid being located on at least 15% and at most 90% of the second line segment as viewed in the thickness direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the second conductor is disposed to avoid being located on at least 15% and at most 90% of the second line segment as viewed in the thickness direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 so as to “provide a semiconductor module that can reduce gate-source inductance and suppress fluctuations of the inductance.” (Kato, [0007])
Regarding claim 13, Kato discloses the semiconductor device according to claim 11, wherein the second conductor (annotated above) includes two second mounting portions (portion of 23a/23b under semiconductor elements 3b/3d) on which the two second semiconductor elements (3b/3d) are mounted, (Fig. 1)
the two second mounting portions (23a/23b) are disposed with a second gap interposed therebetween in the first direction (x-direction), and the second gap intersects the second line segment (from center of 3b to center of 3d) as viewed in the thickness direction. (Fig. 1)
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al. (US 20210280556 A1) as applied to claim 13 above, and further in view of Hayashiguchi (US 20220254758 A1).
Regarding claim 14, Kato discloses the semiconductor device according to claim 13. Kato does not disclose wherein the second conductor includes a second connecting portion connected to both of the two second mounting portions,
the second connecting portion is located in the first sense of the second direction from the second line segment, and
the two first connecting members are each connected to the second connecting portion.
However, Hayashiguchi discloses:
the second conductor (223) includes a second connecting portion (223a) connected to both of the two second mounting portions (223 under 13),
the second connecting portion (223a) is located in the first sense of the second direction (y-direction) from the second line segment (from center of first 13 to center of second 13), and
the two first connecting members (62) are each connected to the second connecting portion (223a). (Fig. 10)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kato and Hayashiguchi for the second conductor includes a second connecting portion connected to both of the two second mounting portions, the second connecting portion is located in the first sense of the second direction from the second line segment, and the two first connecting members are each connected to the second connecting portion in order to “improve the short-circuit tolerance of the semiconductor element.” (Hayashiguchi, [0008])
Regarding claim 15, Hayashiguchi discloses the semiconductor device according to claim 14, wherein each of the two second semiconductor elements (11) includes a second-element obverse surface (11a) and a second-element reverse surface (11b) spaced apart in the thickness direction, ([0033], Fig. 13)
the fourth electrode (112) is disposed on the second-element reverse surface (11b), ([0035], Fig. 13)
the fifth electrode (111) and the sixth electrode (113) are disposed on the second-element obverse surface (11a), ([0035], Fig. 11 and 13) and
each of the two second semiconductor elements (11) is disposed with the second-element reverse (11b) surface facing the second conductor (223). (Fig. 13)
Regarding claim 16, Hayashiguchi discloses the semiconductor device according to claim 15, further comprising:
a third conductor (221) spaced apart from the first conductor (226) and the second conductor
(223); ([0045], Fig. 10)
two second connecting members (61) electrically connecting the third conductor (221) and the fifth electrode (111) of each of the two second semiconductor elements (11); Fig. 11) and
a third power terminal (32) electrically connected to the third conductor (221) and electrically conducting to the fifth electrodes (111) of the two second semiconductor elements (11). (Fig. 10)
Regarding claim 17, Hayashiguchi discloses the semiconductor device according to claim 16, wherein the first power terminal (36) and the third power terminal (32) are input terminals for a direct-current power, ([0109], Fig. 10)
the direct-current power is converted to an alternating-current power by the two first semiconductor elements and the two second semiconductor elements each switching between the on-state and the off-state, ([0109]) and
the second power terminal (31) is an output terminal for the alternating-current power. ([0109], Fig. 10)
Regarding claim 18, Hayashiguchi discloses the semiconductor device according to claim 17, further comprising an insulating substrate (21) supporting the first conductor (226), the second conductor (223), and the third conductor (221). ([0041], Fig. 10)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hatai et al. (US 20130056755 A1) discloses first and second semiconductor elements being mounted on a substrate with gaps between each element in order to enhance the offset effect of the conductor inductances on the front and the rear of the substrate and further enhancing the reduction effect of noise and surges. (per [0048]) but does not disclose some limitations as required by the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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