CTNF 18/440,581 CTNF 86451 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-3, 6, 8, and 10-19 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0161326) in view of Hashimoto (US 2022/0052071) . In reference to claim 1, Oh et al. (US 2020/0161326), hereafter “Oh,” discloses a microelectronic device, comprising: a stack structure comprising a vertically repeated sequence of material structures comprising insulative structures 42 and conductive structures, 41 arranged in tiers, paragraph 54; a series of stadiums R1-R4 in Figure 13, within the stack structure, each of the stadiums individually comprising at least one staircase with steps provided by individual tiers of a group of the tiers, paragraph 105; and step contacts, not pictured, extending to the steps of the stadiums of the series, paragraph 54, the conductive structures of the group of the tiers individually providing a continuous conductive region across the series of stadiums, (“not divided”) paragraph 106. Oh does not disclose at least two of the step contacts being in electrical contact with a single conductive structure of the conductive structures of the group of the tiers. Hashimoto (US 2022/0052071), hereafter “Hashimoto,” discloses an analogous microelectronic memory device including teaching at least two of the step contacts, CC to uppermost 110(SGD) in Figure 3, being in electrical contact with a single conductive structure 110(SGD) of the conductive structures of the group of the tiers, paragraph 118. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least two of the step contacts to be in electrical contact with a single conductive structure of the conductive structures of the group of the tiers. One would have been motivated to do so in order to reduce the resistance of the conductive structure, paragraph 136. In reference to claim 2, Oh discloses each group of the tiers having individual tiers providing steps of the at least one staircase of the stadiums of the series of stadiums is a unique grouping of the tiers of the stack structure, Figure 6 and paragraphs 62 and 63. In reference to claim 3, Oh discloses for at least one stadium of the series of stadiums, at least some of the individual tiers of the group of the tiers provide multiple of the steps of the at least one staircase, Figure 6 and paragraph 62. In reference to claim 6, Oh discloses neighboring stadiums, of the series of stadiums, are horizontally spaced from one another by a crest portion of the stack structure, Figure 6. In reference to claim 8, Oh discloses for at least some of the stadiums of the series of stadiums, the at least one staircase comprises a pair of staircases having substantially mirrored profiles, Figure 6 and paragraph 62. In reference to claim 10, Oh discloses wherein the at least one staircase defines a rise from one of the steps to a neighboring one of the steps of a height of at least one of the tiers, (one tier) Figure 6 and paragraph 62. In reference to claim 11, Yip discloses wherein the at least one staircase defines a rise from one of the steps to a neighboring one of the steps of a height of a single one of the tiers, (one tier) Figure 6 and paragraph 62. In reference to claim 12, Yip discloses each of the tiers consists of a single one of the insulative structures and a single one of the conductive structures, the single one of the insulative structures comprising at least one insulative material, and the single one of the conductive structures comprising at least one conductive material, paragraph 62. In reference to claim 13, Oh discloses a microelectronic device, comprising: a stack structure comprising a vertically repeated sequence of material structures comprising insulative structures 42 and conductive structures 41 arranged in tiers, paragraph 54; at least one block, MB1 defined in the stack structure, the at least one block individually comprising staircased stadiums, R1-R4 in Figure 13, arranged in a row, paragraphs 58 and 105, the staircased stadiums individually comprising: steps provided by individual tiers of a group of the tiers of the stack structure, within the group of the tiers, each of the conductive structures of the tiers individually providing a substantially continuous conductive region along the row (“not divided”) paragraph 106; and step contacts (not pictured) in physical contact with the conductive structures of the tiers providing the steps, paragraph 54, Oh does not disclose for at least some of the conductive structures of the tiers providing the steps, the at least some of the conductive structures individually physical contacting multiple of the step contacts. Hashimoto discloses an analogous microelectronic memory device including teaching for at least some of the conductive structures of the tiers providing the steps, the at least some of the conductive structures, 110(SGD) in Figure 3, individually physical contacting multiple of the step contacts CC, paragraph 118. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least some of the conductive structures of the tiers providing the steps, the at least some of the conductive structures individually physical contacting multiple of the step contacts. One would have been motivated to do so in order to reduce the resistance of the conductive structure, paragraph 136. In reference to claim 14, Oh discloses a bridge portion of the stack structure extends along the row of staircased stadiums, (“the stepped grooves R 1 to R 4 do not divide the conductive layers 41 ”) paragraph 106. In reference to claim 15, Oh discloses the staircased stadiums further individually comprise multiple staircases comprising the steps provided by the individual tiers of the group of the tiers, Figure 6 and paragraphs 62 and 63. In reference to claim 16, Hashimoto discloses for at least some other of the conductive structures, 110(WL) of the tiers providing the steps, the least some other of the conductive structures individually physically contact only one of the step contacts CC, Figure 3. In reference to claim 17, Oh discloses a method of forming a microelectronic device, the method comprising: forming a stack structure comprising a vertically repeated sequence of material structures comprising insulative structures 42 and other structures 41 arranged in tiers, paragraph 54; forming within upper elevations of the stack structure a series of stadium openings defining staircase profiles, R1-R4 in Figure 6 and 20A; extending deeper into the stack structure the staircase profiles of at least some of the stadium openings of the series to define a series of stadiums within the stack structure, each of the stadiums individually comprising at least one staircase with steps provided by individual tiers of a group of the tiers, Figures 20C-20E, paragraphs 62, 63, 142, 147, and 153 ; and forming step contacts (not pictured) extending to the steps of the stadiums of the series, paragraph 54; wherein forming the stack structure comprises either: forming at least one conductive material to form the other structures as conductive structures; or forming at least one sacrificial material to form the other structures as sacrificial structures, and then substantially replacing or converting the at least one sacrificial material with the at least one conductive material to form the conductive structures, paragraph 162; and wherein the conductive structures of the group of the tiers individually provide a continuous conductive region across the series of stadiums, (“not divided”) paragraph 106. Oh does not disclose wherein at least two of the step contacts are in electrical contact with a single conductive structure of the conductive structures of the group of the tiers. Hashimoto discloses an analogous microelectronic memory device including teaching at least two of the step contacts, CC in Figure 3, are in electrical contact with a single conductive structure 110(SGD) of the conductive structures of the group of the tiers, paragraph 118. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least two of the step contacts to be in electrical contact with a single conductive structure of the conductive structures of the group of the tiers. One would have been motivated to do so in order to reduce the resistance of the conductive structure, paragraph 136. In reference to claim 18, Oh discloses forming the stack structure comprises the forming of the at least one sacrificial material and then the substantially replacing or converting of the at least one sacrificial material with the at least one conductive material to form the conductive structures, paragraph 162; and extending deeper into the stack structure the staircase profiles, Figure 20E, precedes the substantially replacing or converting of the at least one sacrificial material with the at least one conductive material, Figure 20G (from Figure 20F to 20G, 51 and 52 go to 41 and 42). In reference to claim 19, Oh discloses forming the stack structure comprises the forming of the at least one sacrificial material and then the substantially replacing or converting of the at least one sacrificial material with the at least one conductive material to form the conductive structures; and the substantially replacing or converting of the at least one sacrificial material with the at least one conductive material precedes forming the step contacts, paragraphs 162 and 54 (“vertical contacts may be landed on the pad regions of the conductive layers 41 and connected to the conductive layers”) . 07-22-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0161326) in view of Hashimoto (US 2022/0052071) as applied to claim 1 above and further in view of Lee (US 2020/0294850) . In reference to claim 4, Oh does not disclose for at least two stadiums of the series of stadiums, the group of the tiers providing the steps of the at least one staircase of one of the at least two stadiums is a same group of the tiers providing the steps of the at least one staircase of another of the at least two stadiums. Lee (US 2020/0294850) discloses an analogous microelectronic memory device including teaching for at least two stadiums, T11 and T12 in Figure 2A, of the series of stadiums, the group of the tiers providing the steps of the at least one staircase of one of the at least two stadiums is a same group of the tiers providing the steps of the at least one staircase of another of the at least two stadiums, paragraphs 42, 56, and 57. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for, for at least two stadiums of the series of stadiums, the group of the tiers providing the steps of the at least one staircase of one of the at least two stadiums is a same group of the tiers providing the steps of the at least one staircase of another of the at least two stadiums. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one stair configuration for another . 07-22-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0161326) in view of Hashimoto (US 2022/0052071) as applied to claim 1 above and further in view of Lee et al. (US 2020/0227434) . In reference to claim 5, Oh does not disclose in at least one stadium of the series of stadiums, the steps define a greater horizontal surface area than the steps in at least one other stadium of the series of stadiums. Lee et al. (US 2020/0227434) discloses an analogous microelectronic memory device including teaching in at least one stadium of the series of stadiums, the steps US1, US2 in Figure 2, define a greater horizontal surface area than the steps MS1, MS2 in at least one other stadium of the series of stadiums. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for, in at least one stadium of the series of stadiums, the steps define a greater horizontal surface area than the steps in at least one other stadium of the series of stadiums. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one stair configuration for another . 07-22-aia AIA Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0161326) in view of Hashimoto (US 2022/0052071) as applied to claim 1 above and further in view of Yip et al. (US 2015/0001613) . In reference to claim 7, Oh discloses conductive contacts, CP in Figure 7, disposed outside of a horizontal area of the stadiums of the series of stadiums (in OP, Figure 13), paragraphs 54, 55, 110, 111. Oh is silent regarding the conductive contact being in electrical communication with the step contacts. Yip et al. (US 2015/0001613), hereafter “Yip,” discloses an analogous microelectronic memory device including teaching conductive contacts, 311A in Figure 4, disposed outside of a horizontal area of the stadiums of the series of stadiums, the conductive contacts being in electrical communication with the step contacts, paragraph 43. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the conductive contact to be in electrical communication with the step contacts. One would have been motivated to do so in order to connect the conductive layers to control circuitry, paragraph 43 of Yip, as suggested by Oh, paragraph 54 . 07-22-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0161326) in view of Hashimoto (US 2022/0052071) as applied to claim 1 above and further in view of Zhang et al. (US 2021/0296232) . In reference to claim 9, Oh does not disclose for at least some of the stadiums of the series of stadiums, the at least one staircase comprises a pair of vertically offset staircases. Zhang et a. (US 2021/00296232) discloses an analogous microelectronic memory device including teaching for at least some of the stadiums of the series of stadiums, the at least one staircase comprises a pair of vertically offset staircases, 406-1 and 406-2 in Figure 4, for example, paragraphs 44 and 45. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for at least some of the stadiums of the series of stadiums, the at least one staircase comprises a pair of vertically offset staircases. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one stair configuration for another . 07-22-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2020/0161326) in view of Hashimoto (US 2022/0052071) as applied to claim 17 above and further in view of Hwang et al. (US 20200135749) . In reference to claim 20, Oh does not disclose forming within the upper elevations of the stack structure the series of stadium openings comprises, for individual of the stadium openings of the series of stadium openings, defining a pair of staircase profiles that are substantially mirrored to one another; and extending deeper into the stack structure the staircase profiles of the at least some of the stadium openings of the series comprises: for at least some of the individual of the stadium openings of the series of stadium openings, vertically offsetting one staircase profile of the pair of staircase profiles from another staircase profile of the pair of staircase profiles; and for at least some other of the individual of the stadium openings of the series of stadium openings, maintaining the substantial mirroring of the stadium profiles of the pair of staircase profiles when extending the staircase profiles deeper into the stack structures is complete. Hwang et al. (US 20200135749) discloses an analogous method of making a microelectronic memory device including teaching forming within the upper elevations of the stack structure the series of stadium openings comprises, for individual of the stadium openings of the series of stadium openings, defining a pair of staircase profiles that are substantially mirrored to one another; and extending deeper into the stack structure the staircase profiles of the at least some of the stadium openings of the series comprises: for at least some of the individual of the stadium openings of the series of stadium openings, vertically offsetting one staircase profile of the pair of staircase profiles from another staircase profile of the pair of staircase profiles, right side in Figure 4B; and for at least some other of the individual of the stadium openings of the series of stadium openings, maintaining the substantial mirroring of the stadium profiles of the pair of staircase profiles when extending the staircase profiles deeper into the stack structures is complete, left side in Figure 4B, see also Figures 27A-E. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for forming within the upper elevations of the stack structure the series of stadium openings comprises, for individual of the stadium openings of the series of stadium openings, defining a pair of staircase profiles that are substantially mirrored to one another; and extending deeper into the stack structure the staircase profiles of the at least some of the stadium openings of the series comprises: for at least some of the individual of the stadium openings of the series of stadium openings, vertically offsetting one staircase profile of the pair of staircase profiles from another staircase profile of the pair of staircase profiles; and for at least some other of the individual of the stadium openings of the series of stadium openings, maintaining the substantial mirroring of the stadium profiles of the pair of staircase profiles when extending the staircase profiles deeper into the stack structures is complete. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one stair configuration for another . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (US 2019/0139978) Fig. 15A, Lee (US 2017/0317088), Fig. 2A, 2B, Futatsuyama (US 10,957,368), Lee (US 2017/0373088), Lee (US 10,373,970) and Lee et al. (US 2017/0250194) disclose at least two step contacts in contact with a same conductive layer, albeit not a single conductive structure . Kim et al. (US 2020/0295028), Lee (US 2017/0033117), and Hwang et al. (US 2013/0161821) disclose related stairstep structures. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRYAN R JUNGE/ Primary Examiner, Art Unit 2897 Application/Control Number: 18/440,581 Page 2 Art Unit: 2897 Application/Control Number: 18/440,581 Page 3 Art Unit: 2897 Application/Control Number: 18/440,581 Page 4 Art Unit: 2897 Application/Control Number: 18/440,581 Page 5 Art Unit: 2897 Application/Control Number: 18/440,581 Page 6 Art Unit: 2897 Application/Control Number: 18/440,581 Page 7 Art Unit: 2897 Application/Control Number: 18/440,581 Page 10 Art Unit: 2897 Application/Control Number: 18/440,581 Page 11 Art Unit: 2897 Application/Control Number: 18/440,581 Page 12 Art Unit: 2897 Application/Control Number: 18/440,581 Page 13 Art Unit: 2897 Application/Control Number: 18/440,581 Page 14 Art Unit: 2897
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