DETAILED ACTION
This action is responsive to the election received on 05/27/2026
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species C (Figure 3) in the reply filed on 05/27/2026 is acknowledged. Claim(s) 1-6 and 19-25 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/21/2024, 05/09/2025, and 12/18/2025 has/have been considered by the examiner and made of record in the application file.
Claim Objections
Claim(s) 8-10 and 14-15 is/are objected to because of the following informalities:
Claim 8, line 2, “is less than a height of the pad level dielectric” where height appears to be misspelled;
Claim 14, line 2, “is less than a height of the pad level dielectric” where height appears to be misspelled.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 7-18 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7-11, 13-15, and 17 recite limitations for which there is insufficient antecedent basis for the limitations in the claims. All remaining listed claims are rejected under 35 U.S.C. 112(b) at least for their dependencies. The examiner has attempted to identify all such issues of antecedent basis along with explanation and proposed amendments (bolded and underlined) in an effort to provide proper antecedent basis for the limitations:
Claim 7, line 5, “a first e-fuse terminal in the [[first]] lower semiconductor build” as there has been no previous recitation of a first semiconductor build such that it is unclear if this is a new element or is referencing the lower/upper semiconductor builds identified earlier in the claim(s);
Claim 8, line 2, “is less than a heigh of the pad level dielectric layer” as there has been no previous recitation of a pad level dielectric such that it is unclear if this is a new element or is referencing the pad level dielectric layer identified earlier in the claim(s);
Claim 9, line 2, “covered by the pad level dielectric layer” as there has been no previous recitation of a pad dielectric such that it is unclear if this is a new element or is referencing the pad level dielectric layer identified earlier in the claim(s);
Claim 10, lines 1-2, “the top surface of the first e-fuse terminal” as there has been no previous recitation of a first terminal such that it is unclear if this is a new element or is referencing the first e-fuse terminal identified earlier in the claim(s);
Claim 10, line 2, “coplanar with the pad level dielectric layer” as there has been no previous recitation of a pad dielectric such that it is unclear if this is a new element or is referencing the pad level dielectric layer identified earlier in the claim(s);
Claim 11, lines 1-2, “adjacent to the e-fuse link” as there has been no previous recitation of a fuse such that it is unclear if this is a new element or is referencing the e-fuse link identified earlier in the claim(s);
Claim 13, line 5, “a first e-fuse terminal in the [[first]] lower semiconductor build” as there has been no previous recitation of a first semiconductor build such that it is unclear if this is a new element or is referencing the lower/upper semiconductor builds identified earlier in the claim(s);
Claim 14, line 2, “is less than a heigh of the pad level dielectric layer” as there has been no previous recitation of a pad level dielectric such that it is unclear if this is a new element or is referencing the pad level dielectric layer identified earlier in the claim(s);
Claim 15, line 2, “covered by the pad level dielectric layer” as there has been no previous recitation of a pad dielectric such that it is unclear if this is a new element or is referencing the pad level dielectric layer identified earlier in the claim(s);
Claim 17, line 2, “adjacent to the e-fuse link” as there has been no previous recitation of a fuse such that it is unclear if this is a new element or is referencing the e-fuse link identified earlier in the claim(s).
Regarding claim(s) 12 and 18, the term "thin" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Thin” is defined as “having little extent from one surface to its opposite” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how little the extent of the metal trace needs to be in order to be considered “thin”. The term “thin” is a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “thin” any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (such as several nm, µm, or mm), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, claim (s) 12 and 18 is/are rejected as being indefinite under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. For the purposes of this examination, it will be interpreted that any metal trace in a semiconductor device is thin as it is on the small scale of semiconductor devices.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 7-10, 12-16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0165665 A1; Chang et al.; 05/2022; (“Chang”).
Regarding Claim 7. Chang discloses A hybrid bonded semiconductor structure (Figure 8) comprising:
a lower semiconductor build (#102, Figure 8, first integrated circuit component);
an upper semiconductor build (#104, Figure 8, second integrated circuit component) on the lower semiconductor build (Figure 8, #104 is on #102);
a joining interface (Figure 8, interface of the top surface of #102 (top surface of #220) and bottom surface of #104 (bottom surface of #430)) where the lower and upper semiconductor builds meet (Figure 8, #102 and #104 meet at the identified interface);
a first e-fuse terminal (#224 far right, Figure 8, conductive pattern) in the [[first]] lower semiconductor build (Figure 8, #224 on the far right is located in #102);
a second e-fuse terminal (#222a and #432, Figure 8, bonding pads) comprising an upper contact pad in the upper semiconductor build (Figure 8, #432 is located in #104) in contact with a lower contact pad in the lower semiconductor build (Figure 8, #222a located in #102 and which #432 is in direct contact with); and
an e-fuse link (#230, Figure 8, fuse structure) between the first and second e-fuse terminals (Figure 8, #230 is located between #224 on the far right and the combination of #432 and #222a on the left thereof).
Regarding Claim 8. Chang discloses The hybrid bonded semiconductor structure of claim 7, further comprising a pad level dielectric layer (#220, Figure 8, bonding layer made of dielectric material according to [0026]) wherein a height of the e-fuse link is less than a height of the pad level dielectric layer (Figure 8, a vertical height of #230 is less than a vertical height of #220).
Regarding Claim 9. Chang discloses The hybrid bonded semiconductor structure of claim 8, wherein a top surface of the e-fuse link is covered by the pad level dielectric layer (Figure 8, a top surface of #230 is covered at least partially by #220).
Regarding Claim 10. Chang discloses The hybrid bonded semiconductor structure of claim 8, wherein the top surface of the first e-fuse terminal is coplanar with the pad level dielectric layer (Figure 8, a top surface of #224 on the far right is coplanar with a top surface of #220).
Regarding Claim 12. Chang discloses The hybrid bonded semiconductor structure of claim 7, wherein the e-fuse link (#230) is selected from the group consisting of thin metal trace, conductive doped oxides, conductive silicides, or other electrically conductive materials ([0030], #230 is made of an electrically conductive material).
Regarding Claim 13. Chang discloses A hybrid bonded semiconductor structure (Figure 8) comprising:
a lower semiconductor build (#102, Figure 8, first integrated circuit component);
an upper semiconductor build (#104, Figure 8, second integrated circuit component) on the lower semiconductor build (Figure 8, #104 is on #102);
a joining interface (Figure 8, interface of the top surface of #102 (top surface of #220) and bottom surface of #104 (bottom surface of #430)) where the lower and upper semiconductor builds meet (Figure 8, #102 and #104 meet at the identified interface);
a first e-fuse terminal (#204 far right, Figure 8, interconnection structure) in the [[first]] lower semiconductor build (Figure 8, #204 is located in #102);
a second e-fuse terminal (#222a and #432, Figure 8, bonding pads) comprising an upper contact pad in the upper semiconductor build (Figure 8, #432 is located in #104) in contact with a lower contact pad in the lower semiconductor build (Figure 8, #222a located in #102 and which #432 is in direct contact with); and
an e-fuse link (#230, Figure 8, fuse structure) between the first and second e-fuse terminals (Figure 8, #230 is located between #204 on the far right and the combination of #432 and #222a on the left thereof);
wherein the top surface of the first terminal is at least partially covered by the e-fuse link (Figures 3A-3C show schematic views which are further described in [0028]-[0031], these figures show that the fuse structure is formed to at least partially cover a top surface of the conductive contact 212-1, see [0029] and Figure 3B, “fuse structure 230 is formed over the conductive portions 222a-1 and 212-1”).
Regarding Claim 14. Chang discloses The hybrid bonded semiconductor structure of claim 13,
further comprising a pad level dielectric layer (#220, Figure 8, bonding layer made of dielectric material according to [0026]) wherein a height of the e-fuse link is less than a height of the pad level dielectric layer (Figure 8, a vertical height of #230 is less than a vertical height of #220).
Regarding Claim 15. Chang discloses The hybrid bonded semiconductor structure of claim 14, wherein at least a portion of a top surface of the e-fuse link is covered by the pad level dielectric layer (Figure 8, a top surface of #230 is covered at least partially by #220).
Regarding Claim 16. Chang discloses The hybrid bonded semiconductor structure of claim 13, wherein at least another portion of the top surface of the e-fuse link is covered by the lower contact pad (Figures 3A-3C show schematic views which are further described in [0028]-[0031], these figures show that the top surface of the fuse structure is at least partially covered by #222a-2, see [0031], [0044], and Figure 3C, i.e. #432 has a bottom surface which at least partially covers the top surface of #230).
Regarding Claim 18. Chang discloses The hybrid bonded semiconductor structure of claim 13, wherein the e-fuse link (#230) is selected from the group consisting of thin metal trace, conductive doped oxides, conductive silicides, or other electrically conductive materials ([0030], #230 is made of an electrically conductive material).
Claim(s) 7-8, 10, 12-15, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2014/0210040 A1; Filippi et al.; 07/2014; (“Filippi”).
Regarding Claim 7. Filippi discloses A hybrid bonded semiconductor structure (Figure 11, e-fuse structure which may be formed in semiconductor devices according to [0029]) comprising:
a lower semiconductor build (#240 and #202, Figure 11, lower metal level and middle metal level);
an upper semiconductor build (#218, Figure 11, upper metal level) on the lower semiconductor build (Figure 11, #218 is located on the combination of #240 and #202);
a joining interface where the lower and upper semiconductor builds meet (Figure 11, interface of #214/#210 and #220);
a first e-fuse terminal (#248, Figure 11, fourth via) in the [[first]] lower semiconductor build (Figure 11, #248 is located in the combination of #240 and #202);
a second e-fuse terminal comprising an upper contact pad (#228, Figure 11, metal line) in the upper semiconductor build (Figure 11, #228 is located in #218) in contact with a lower contact pad (#232, Figure 11, second via in contact with #228) in the lower semiconductor build (Figure 11, #232 is located at least partially in #202); and
an e-fuse link (#208, Figure 11, fuse line) between the first and second e-fuse terminals (Figure 11, #208 is located between #248 and the combination of #228 and #232).
Regarding Claim 8. Filippi discloses The hybrid bonded semiconductor structure of claim 7, further comprising a pad level dielectric layer (#204, Figure 11, dielectric layer) wherein a height of the e-fuse link is less than a height of the pad level dielectric layer (Figure 11, a vertical height of #204 is greater than the vertical height of #208).
Regarding Claim 10. Filippi discloses The hybrid bonded semiconductor structure of claim 8, wherein the top surface of the first e-fuse terminal is coplanar with the pad level dielectric layer (Figure 11, the top surface of #248 is coplanar with the top surface of #204 on the bottom of #208).
Regarding Claim 12. Filippi discloses The hybrid bonded semiconductor structure of claim 7, wherein the e-fuse link is selected from the group consisting of thin metal trace, conductive doped oxides, conductive silicides, or other electrically conductive materials ([0035], #208 may be made of a plurality of different conductive materials).
Regarding Claim 13. Filippi discloses A hybrid bonded semiconductor structure (Figure 11, e-fuse structure which may be formed in semiconductor devices according to [0029]) comprising:
a lower semiconductor build (#240 and #202, Figure 11, lower metal level and middle metal level);
an upper semiconductor build (#218, Figure 11, upper metal level) on the lower semiconductor build (Figure 11, #218 is located on the combination of #240 and #202);
a joining interface where the lower and upper semiconductor builds meet (Figure 11, interface of #214/#210 and #220);
a first e-fuse terminal (#248, Figure 11, fourth via) in the [[first]] lower semiconductor build (Figure 11, #248 is located in the combination of #240 and #202);
a second e-fuse terminal comprising an upper contact pad (#228, Figure 11, metal line) in the upper semiconductor build (Figure 11, #228 is located in #218) in contact with a lower contact pad (#232, Figure 11, second via in contact with #228) in the lower semiconductor build (Figure 11, #232 is located at least partially in #202); and
an e-fuse link (#208, Figure 11, fuse line) between the first and second e-fuse terminals (Figure 11, #208 is located between #248 and the combination of #228 and #232);
wherein the top surface of the first terminal is at least partially covered by the e-fuse link (Figure 11, the top surface of #248 is at least partially covered by #208).
Regarding Claim 14. Filippi discloses The hybrid bonded semiconductor structure of claim 13, further comprising a pad level dielectric layer (#204, Figure 11, dielectric layer) wherein a height of the e-fuse link is less than a height of the pad level dielectric layer (Figure 11, a vertical height of #204 is greater than the vertical height of #208).
Regarding Claim 16. Filippi discloses The hybrid bonded semiconductor structure of claim 13, wherein at least another portion of the top surface of the e-fuse link is covered by the lower contact pad (Figure 11, a portion of the top surface of #208 is covered by #232).
Regarding Claim 18. Filippi discloses The hybrid bonded semiconductor structure of claim 13, wherein the e-fuse link is selected from the group consisting of thin metal trace, conductive doped oxides, conductive silicides, or other electrically conductive materials ([0035], #208 may be made of a plurality of different conductive materials).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165665 A1; Chang et al.; 05/2022; (“Chang”) as applied to claim(s) 7 and 13 above, and further in view of US 2024/0162146 A1; Pandey et al.; 05/2024; (“Pandey”).
Regarding Claim 11. Chang discloses The hybrid bonded semiconductor structure of claim 7.
Chang does not appear to disclose a heater adjacent to the e-fuse link.
However, Pandey teaches a semiconductor structure (Figure 9) comprising an e-fuse (#16) with electrical contacts (#28) provided to electrically connect to opposing ends of the e-fuse and an e-fuse link (#16b) therebetween, and a heater (#14) is provided adjacent to the e-fuse link.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing a heater adjacent to the e-fuse link in Chang as was done in Pandey since the inclusion of a heater because “heat from the heaters 14 to the e-fuse 16 which will effectively allow a lower e-fuse programming current (e.g., >=10% reduction in blow current) and, in turn, may also reduce chip area for e-fuse circuitry” (see [0014] of Pandey)
Regarding Claim 17. Chang discloses The hybrid bonded semiconductor structure of claim 13.
Chang does not appear to disclose a heater adjacent to the e-fuse link.
However, Pandey teaches a semiconductor structure (Figure 9) comprising an e-fuse (#16) with electrical contacts (#28) provided to electrically connect to opposing ends of the e-fuse and an e-fuse link (#16b) therebetween, and a heater (#14) is provided adjacent to the e-fuse link.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing a heater adjacent to the e-fuse link in Chang as was done in Pandey since the inclusion of a heater because “heat from the heaters 14 to the e-fuse 16 which will effectively allow a lower e-fuse programming current (e.g., >=10% reduction in blow current) and, in turn, may also reduce chip area for e-fuse circuitry” (see [0014] of Pandey)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2012/0306048 A1; Li et al.; 12/2012 – Figure 2 discloses an e-fuse structure (#100) comprising upper and lower terminals (#52s) connected by an e-fuse link (#50) between an upper and lower semiconductor build (#15 and #95) and further comprising adjacent heaters (#70 and #30) to confine heat generated during programming (see [0040]).
Pre-bond testing of the silicon interposer in 2.5D ICs; Wang et al.; 2016 – Figure 5 discloses an e-fuse structure including e-fuse terminals (interconnects) connected by an e-fuse link (#b) to provide electrical connections between upper and lower semiconductor builds.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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