Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claim 1-13 in the reply filed on May 13, 2026 is acknowledged. Claims 14-19 are withdrawn as being directed to a nonelected invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 20200135683).
Kim et al teaches
[claim 1] A semiconductor device comprising: a first chip including a first chip body and a first bonding layer disposed on the first chip body, the first bonding layer including a first bonding pad (figure 7, paragraphs 0024 and 0056, where element 226 is the first bonding layer on the first chip [element 120], where the first chip has a first chip body [element 121], where the first bonding layer [226] has a first bonding pad [element 226P]),
and a second chip bonded on the first bonding layer, the second chip including a second chip body and a second bonding layer disposed under the second chip body, wherein the second bonding layer includes a second bonding pad bonded to the first bonding pad (figure 7, paragraphs 0053 and 0056, where element 220b is the second chip, element 221b is the body portion of the second chip, where the second chip has a second bonding layer [element 227] with a second bonding pad [element 227p] which is connected to the first bonding pad [element 226p]),
wherein a side surface of the first bonding layer and a side surface of the second chip are retracted inward of a side surface of the first chip body (figure 7, paragraphs 0024 and 0053, where element 226 [first bonding layer], and the second chip [element 220b] have a side surface [left-hand side] retracted inward from the side surface of the first chip [left-hand side of element 120]).
[claim 2] The semiconductor device according to claim 1, further comprising: an insulating member disposed on an edge portion of the first chip body which protrudes beyond the side surface of the first bonding layer and the side surface of the second chip (figure 7, paragraph 0053, where element 240a is the insulating member disposed on an edge portion of the first chip body [element 121] which protrudes beyond the side surface of the first bonding layer [element 226]).
[claim 8] A semiconductor device comprising: a first chip including a first chip body including a device region in which a peripheral circuit is defined and a scribe lane region which surrounds the device region, and a first bonding layer disposed on the first chip body and including a first bonding pad, (figure 7, paragraphs 0024 and 0056, where element 226 is the first bonding layer on the first chip [element 120], where the first chip has a first chip body [element 121], where the first bonding layer [226] has a first bonding pad [element 226P], where the scribe lane is the region surrounding the first chip [best shown by the dotted line in figure 10F that separates the identical forms of figure 7, and the device portion is the central portion of the chip body situated between the left edge and right edge of the device),
and a second chip bonded on the first bonding layer, and including a second bonding layer including a second bonding pad which is bonded to the first bonding pad and a second chip body disposed on the second bonding layer and including a memory cell array (figure 7, paragraphs 0053 and 0056, where element 220b is the second chip, element 221b is the body portion of the second chip, where the second chip has a second bonding layer [element 227] with a second bonding pad [element 227p] which is connected to the first bonding pad [element 226p]),
wherein the first bonding layer and the second chip overlap with the device region of the first chip body, and do not overlap with the scribe lane region of the first chip body (figure 7, paragraph 0053, where the first bonding layer [element 226] and the second chip [element 220b] overlap the central region of the first chip [device region] but do not overlap the outer portion [shown best by the dotted line in figure 10F]).
[claim 9] The semiconductor device according to claim 8, further comprising: an insulating member disposed on the scribe lane region of the first chip body and the second chip, and covering a side surface of the first bonding layer and a top surface and a side surface of the second chip (figure 7, paragraphs 0053 and 0069, where element 240a and 255 comprise an insulating member which is disposed over the scribe region [edge portion of the semiconductor stack as shown in figure 10F], covers the side-wall of the second chip [element 220b] and the first-bonding layer [element 226] and the top portion of the second chip).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20200135683).
Kimet al teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 3] The semiconductor device according to claim 2, wherein the insulating member comprises an insulating material with a modulus of rupture smaller than that of the first and second bonding pads.
However, according to MPEP 2144.05 Obviousness of Similar and Overlapping Ranges, Amounts, and Proportions [R-01.2024]
See MPEP § 2131.03 for case law pertaining to rejections based on the anticipation of ranges under 35 U.S.C. 102 and 35 U.S.C. 102 /103.
II. ROUTINE OPTIMIZATION
A. Optimization Within Prior Art Conditions or Through Routine Experimentation
Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989)(Claimed ratios were obvious as being reached by routine procedures and producing predictable results); In re Kulling, 897 F.2d 1147, 1149, 14 USPQ2d 1056, 1058 (Fed. Cir. 1990)(Claimed amount of wash solution was found to be unpatentable as a matter of routine optimization in the pertinent art, further supported by the prior art disclosure of the need to avoid undue amounts of wash solution); and In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good"); Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions."). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416, 82 USPQ2d 1385, 1395 (2007) (identifying "the need for caution in granting a patent based on the combination of elements found in the prior art.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al to optimize the material of insulating members to have a modulus of rupture smaller than the bonding layer. The modulus of rupture could have one of three relative values, greater than, equal to, or less than the chip. To optimize the structural efficiency of the device, it would be obvious to try all three options to ensure the device would be the most structurally stable.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20200135683) in view of Kweon et al (US 20230395547).
Regarding claim 4, Kim et al teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 4] The semiconductor device according to claim 2, wherein the insulating member comprises at least one of oxide, nitride, SiCOH, N-doped SiC (NDC) and any combination thereof.
However, Kweon et al does teach
[claim 4] The semiconductor device according to claim 2, wherein the insulating member comprises at least one of oxide, nitride, SiCOH, N-doped SiC (NDC) and any combination thereof (figure 2, paragraph 0061, where element 314 is the insulating member and is made of silicon nitride, or a combination of silicon nitride with other materials).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al to incorporate the teachings of Kweon et al to insulate the chips to protect it from electrical influences that would make the chip less efficient.
Regarding claim 6, According to another embodiment from Kweon et al,
Kim et al teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 5] The semiconductor device according to claim 2, further comprising: a moisture penetration prevention member disposed between the side surface of the first bonding layer and the insulating member and between the side surface of the second chip and the insulating member.
[claim 6] The semiconductor device according to claim 5, wherein the moisture penetration prevention member comprises nitride.
However, Kweon et al does teach
[claim 5] The semiconductor device according to claim 2, further comprising: a moisture penetration prevention member disposed between the side surface of the first bonding layer and the insulating member and between the side surface of the second chip and the insulating member (figure 2, paragraph 0061, where element 314 is the moisture protection layer, an insulating layer, that is disposed between the side surface of the first bonding layer [element 290 read onto from Kim et al] an the insulating member [element 315, labeled passivation layer but acts as an electrical insulator as well and insulates functionally the same as the insulating layer as read onto from Kim et al] and between the side surface of the second chip [element 230] and the insulating layer [element 315]).
[claim 6] The semiconductor device according to claim 5, wherein the moisture penetration prevention member comprises nitride (figure 2, paragraph 0061, where element 314 is made of silicon nitride, thus contains nitride).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al to incorporate the teachings of Kweon et al to insulate the chips to protect it from electrical influences and degradation from moisture, that would make the chip less efficient.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20200135683) in view of Kim (US 20210159190).
Kim et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 7] The semiconductor device according to claim 1, wherein a top surface of the edge portion of the first chip body which protrudes beyond the side surface of the first bonding layer and the side surface of the second chip is disposed to be lower than a top surface of a center portion of the first chip body which overlaps with the first bonding layer and the second chip.
However, Kim does teach
[claim 7] The semiconductor device according to claim 1, wherein a top surface of the edge portion of the first chip body which protrudes beyond the side surface of the first bonding layer and the side surface of the second chip is disposed to be lower than a top surface of a center portion of the first chip body which overlaps with the first bonding layer and the second chip (figure 7A, paragraph 0061, where element 2011h is the “hollow” portion of the semiconductor body where the top surface of the edge portion of the chip body protrudes beyond a side surface of the first bonding layer and a side surface of the second chip wherein element 2011 is read onto the first chip of Kim et al, and the bonding layer is situated above the first chip where the sidewall of the second chip [from Kim et al] is recessed to the sidewall of the first chip, where the top surface of the edge portion of the first chip is lower than the top portion of the center of the first chip [shown by hallow portion 2011h of figure 7A]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al with the teachings of Kim to create a “hollow” portion in the first semiconductor chip to allow for maximal bonding between the first and second chip without using more material than necessary in order to produce the connected devices with the least amount of necessary material to maximize efficiency of the material.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20200135683) in view of Yang et al (US 20190131277).
Kim et al teaches all of the limitations of the parent claim, claim 8, but does not specifically disclose
[claim 10] The semiconductor device according to claim 8, wherein the first chip body comprises: a substrate; the peripheral circuit disposed on the substrate; a first insulating layer disposed on the substrate, and covering the peripheral circuit; a contact disposed in the device region of the first insulating layer, and directly connected to the first bonding pad; and a dummy contact disposed in the scribe lane region of the first insulating layer, and positioned at the same level as the contact, wherein a top surface of the scribe lane region of the first chip body is disposed at the same level as a top surface of the dummy contact.
[claim 11] The semiconductor device according to claim 8, wherein the first chip body comprises: a substrate; the peripheral circuit disposed on the substrate; a first insulating layer covering the peripheral circuit; an interconnection disposed in the device region of the first insulating layer; and a dummy interconnection disposed in the scribe lane region of the first insulating layer, and positioned at the same level as the interconnection, wherein a top surface of the scribe lane region of the first chip body is disposed at the same level as a top surface of the dummy interconnection.
However, Yang et al teaches
[claim 10] The semiconductor device according to claim 8, wherein the first chip body comprises: a substrate; the peripheral circuit disposed on the substrate (figure 1E, paragraph 0036, where element 200 with element 15 comprises the first chip [as read onto from Kim et al], where element 202 is the substrate, and the peripheral circuit [element 203] is disposed on the substrate);
a first insulating layer disposed on the substrate, and covering the peripheral circuit (figure 1E, paragraphs 0040 and 0043, where elements 128 and 140a comprise the insulating layer disposed on the substrate and covers the peripheral circuit);
a contact disposed in the device region of the first insulating layer, and directly connected to the first bonding pad (figure 1E, paragraph 0041, where element 130 [and the connecting parts directly below] is disposed in the device region of the first insulating layer [element 140a part of the first insulating layer] and connected directly to the first bonding pad [element 122 – shown in figure 1D]);
and a dummy contact disposed in the scribe lane region of the first insulating layer, and positioned at the same level as the contact, wherein a top surface of the scribe lane region of the first chip body is disposed at the same level as a top surface of the dummy contact (figure 1E, paragraph 0042, where element 132 [and parts above such as connection to 140b] is the dummy contact disposed in a scribe lane region [region that is directly below element 128 – contains the outer portion of the devices] where the top surface of the scribe lane region [including elements 128 and 140a] is at the same level as a top region of the dummy contact [element 132 and 140b]).
[claim 11] The semiconductor device according to claim 8, wherein the first chip body comprises: a substrate; the peripheral circuit disposed on the substrate (figure 1E, paragraph 0036, where element 200 with element 15 comprises the first chip [as read onto from Kim et al], where element 202 is the substrate, and the peripheral circuit [element 203] is disposed on the substrate);
a first insulating layer covering the peripheral circuit (figure 1E, paragraphs 0040 and 0043, where elements 128 and 140a comprise the insulating layer disposed on the substrate and covers the peripheral circuit);
an interconnection disposed in the device region of the first insulating layer (figure 1D, paragraph 0037,where element 224 and 226 disposed underneath the second die [element 104 and 102] in element 215 is the first interconnection structure disposed in the device region);
and a dummy interconnection disposed in the scribe lane region of the first insulating layer, and positioned at the same level as the interconnection (figures 1E and 1D, paragraph 0042, where element 226 and 224 underneath element 128 in the first chip region [element 200 and 15] is the dummy interconnection disposed in the scribe lane region [section encapsulated by element 128 in a vertical direction] and disposed in the first insulating layer [element 128 and element 140a] and positioned at a same level as the interconnection [where elements 224 and 226 are at the same level as element 224 and 226 underneath the second chip]);
wherein a top surface of the scribe lane region of the first chip body is disposed at the same level as a top surface of the dummy interconnection (figure 1E, paragraph 0043, where element 215 comprises a part of the body region [with element 204] and has a top portion equal to the top portion of element 226 and 224 [dummy interconnection]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al to incorporate the teachings of Yang et al in order to insert interconnects within the first and second chips to allow connection between the circuits within the semiconductor device and any outside device to form a functioning semiconductor device.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20200135683) in view of Baraskara et al (US 20210082865).
Kim et al teaches all of the limitations of the parent claim, claim 8, but does not specifically disclose,
[claim 12] The semiconductor device according to claim 8, wherein the second chip body comprises: a first insulating layer disposed on the second bonding layer; a stack disposed on the first insulating layer, and including a plurality of interlayer insulating layers and a plurality of electrode layers alternately stacked along a cell plug which extends in a vertical direction; a second insulating layer disposed on the first insulating layer, and surrounding a side surface of the stack; a source plate disposed on the stack; and a third insulating layer disposed on the second insulating layer, and surrounding a side surface of the source plate.
However, Baraskara et al teaches
[claim 12] The semiconductor device according to claim 8, wherein the second chip body comprises: a first insulating layer disposed on the second bonding layer (figure 54, paragraph 0175, where element 960 is the first insulating layer disposed on the second bonding layer [elements 980 and 988 that bond the first chip [`1240] to the second chip [1140]);
a stack disposed on the first insulating layer, and including a plurality of interlayer insulating layers and a plurality of electrode layers alternately stacked along a cell plug which extends in a vertical direction (figure 54, paragraphs 0095, 0102, and 0160, where elements 32 and 46 is a stack disposed on the first insulating layer [element 960] and includes a plurality of interlay insulating layers [element 32] and electrode layers [element 46] stacked along a cell plug [element 70] in a vertical direction);
a second insulating layer disposed on the first insulating layer, and surrounding a side surface of the stack (figure 54, paragraph 0107, where element 65 is the second insulating layer disposed on the first insulating layer [element 960] and surrounding a side surface of the stack [element 65 surrounds a side surface of elements 32, 46, 70 combined]);
a source plate disposed on the stack; and a third insulating layer disposed on the second insulating layer, and surrounding a side surface of the source plate (figure 60E, paragraphs 0245 and 0275, where element 1170 I the third insulating layer disposed on a second insulating layer [element 65] and surrounds a side surface of the course plate [element 1120]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al to incorporate the teachings of Baraskara et al in order to place a memory die in the second chip region to integrate a memory portion into a stacked arrangement to allow for shorter connections from memory to logic die or other processing die to maximize efficiency of the die combined stack.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20200135683), and Baraskara et al (US 20210082865) and in further view of Kweon et al (US 20230395547) and Park (US 11211372).
Kim et al as modified teaches all of the limitations of the parent claim, claim 12, but does specifically disclose
[claim 13] The semiconductor device according to claim 12, further comprising: a contact connected to the source plate by passing through the insulating member in the device region; a top interconnection disposed on the insulating member, and connected to the contact; a dummy contact passing through a top surface of the insulating member in the scribe lane region, and disposed at the same level as the contact; and a dummy top interconnection disposed on the insulating member, and connected to the dummy contact.
However, Kweon et al does teach
[claim 13] The semiconductor device, further comprising: a contact connected to the source plate by passing through the insulating member in the device region (figure 2, paragraphs 0028 and 0059, where element 210 is the source plate which is contacted to element 353 [the contact] and passes through an insulating member [element 215] in the device region [region shown in figure 2]);
a top interconnection disposed on the insulating member, and connected to the contact (figure 2, paragraph 0028, where element 360 is the top interconnection disposed on the insulating member [element 215] and connected to the contact [element 353]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al to have modified the teachings of Kweon et al to connect the memory portions of the second chip to the outside through the insulating layer to allow for read and write of the memory device with direct contact to said memory device thus making the chip more efficient.
However, Kim et al as modified does not specifically disclose
[claim 13] a dummy contact passing through a top surface of the insulating member in the scribe lane region, and disposed at the same level as the contact; and a dummy top interconnection disposed on the insulating member, and connected to the dummy contact.
However, Park does teach
[claim 13] a dummy contact passing through a top surface of the insulating member in the scribe lane region, and disposed at the same level as the contact (figure 8B, col 14 lines 12-39, where element PAD is the dummy contact that passes through a top surface of the insulating member [element 294 and 292 read onto from Kweon et al where element 294 and 292 replaces the insulating layer of Kweon et al], in the scribe lane region [region outside the device region of Park as shown to be in the vertical direction of element 260b and does not extend beyond the horizontal confines of element PAD], and disposes at the same level as the contact [where the contact is read onto Park by Kweon et al, where the element PAD of Park would be at the same level as the contact of Kweon et al]);
and a dummy top interconnection disposed on the insulating member, and connected to the dummy contact (figure 8B, col 14 lines 12-39, where element 205E is the dummy top interconnection disposed on the insulating member [element 292 and 294] and connected to the dummy contact [element PAD]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Kim et al as modified to incorporate the teachings of Park to put a dummy contact outside the device region to allow for correct alignment of the devices and processing of multiple devices to maximize spatial efficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al (US 11282816), Song et al (US 20210384161), Lee et al (US 20210358875), Kanamori et al (US 10998301), Hwang et al (US 20200312862), and Kim et al (US 20200243466).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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