Attorney’s Docket Number: SAM-61434
Filing Date: 02/14/2024
Claimed Foreign Priority Date: 07/11/2023 (KR10-2023-0089894)
Applicants: Kim et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 05/11/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1, in the reply filed on 05/11/2026, is acknowledged. However, the restriction requirement between Species 1 and 2, as set forth in the Office action mailed on 03/17/2026, has been reconsidered and is hereby withdrawn. Accordingly, pending in this application are claims 1-20.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Specification
The abstract of the disclosure is objected to because of its excessive length. The abstract must be as concise as the disclosure permits, preferably not exceeding 150 words in length. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 13-14 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 13 recites “wherein a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is less than the sum of areas of at least one of the plurality of first via holes per unit area on the cell region.” at L. 2-4. However, this limitation contradicts the written description (see, e.g., Specification, Par. [0130],[0166]) reciting “The sum of the areas of at least one of the plurality of first via holes H1 per unit area on the pad region THR may be greater than the sum of the areas of at least one of the plurality of first via holes H1 per unit area on the cell region CR.”
The examiner believes that claim 13 should recite instead either --wherein a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is greater than the sum of areas of at least one of the plurality of first via holes per unit area on the cell region --, or -- wherein a sum of areas of at least one of the plurality of second via holes per unit area on the pad region is less than the sum of areas of at least one of the plurality of second via holes per unit area on the cell region.”, in accordance with the disclosure as originally filed. Accordingly, and for the purpose of examination, the claim will be construed as discussed above until further clarifications are provided by applicant.
Claim 14 depends of claim 13 thus inherits the deficiencies identified supra.
Allowable Subject Matter
Claims 1-12 and 15-20 are allowable.
Claims 13 and 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, the prior art fails to disclose of suggest a semiconductor device comprising: wherein the peripheral structure includes: a first barrier structure positioned over the second substrate and including a plurality of lower barrier layers; a plurality of first via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers; a plurality of second via holes disposed on the cell region and penetrating at least one of the plurality of lower barrier layers; and a plurality of contact vias positioned within the plurality of first via holes and connected to the plurality of circuit elements, and wherein, in at least one lower barrier layer of the plurality of lower barrier layers, a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is equal to a sum of areas of at least one of the plurality of first via holes on the cell region and areas of the plurality of second via holes per unit area on the cell region.
Regarding Claim 11, the prior art fails to disclose of suggest a semiconductor device comprising: wherein the peripheral structure includes: a first barrier structure positioned over the second substrate and including a plurality of lower barrier layers; a plurality of first via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers; a plurality of second via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers; and a plurality of contact vias positioned within the plurality of first via holes and connected to the plurality of circuit elements, wherein, in at least one lower barrier layer of the plurality of lower barrier layers, a sum of areas of at least one of the plurality of second via holes per unit area on the cell region is greater than a sum of areas of at least one of the plurality of second via holes per unit area on the pad region.
Regarding Claim 19, the prior art fails to disclose of suggest an electron system comprising: wherein the peripheral structure includes: a first barrier structure disposed on the second substrate and including a plurality of lower barrier layers; a plurality of first via holes disposed on the cell region and the pad region and penetrating at least one of the plurality of lower barrier layers; a plurality of second via holes disposed on the cell region and penetrating at least one of the plurality of lower barrier layers; and a plurality of contact vias positioned within the plurality of first via holes and connected to the plurality of circuit elements, and wherein, in at least one lower barrier layer of the plurality of lower barrier layers, a sum of areas of at least one of the plurality of first via holes per unit area on the pad region is equal to a sum of areas of at least one of the plurality of first via holes on the cell region and areas of the plurality of second via holes per unit area on the cell region.
Examiner’s Comments: The closest prior art reference to Seo (US2024/0315057), Lee et al. (US2023/0389322), Lee et al. (KR20230002161), and Kim et al. (US2021/0407968) disclose memory structures having a cell structure vertically arranged over a peripheral structure comprising barrier layers including via holes, and having most aspects of the instant invention. However, none of the references disclose said peripheral structure having arrangements of barrier layers with first and second holes in cell and pad regions, and having respective sums of areas being limited as identified in the claims supra.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose memory structures having peripheral regions comprising barrier layers including via holes, and having some aspects similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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