DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
The interview filed 07/30/2026 between Applicants representative, Zhang and Examiner Muslim, resulted in no agreement being reached as noted per the interview summary. The Applicant's arguments filed 08/10/2026 have been fully considered but they are not persuasive. The Applicant asserts on page 7 of the Remarks, and through the amended claim 1, that prior art Sumitomo (US 10388773) fails to teach “a control unit configured to turn off the gate electrode in the first trench at different timings than the gate electrode in the second trench.”
The Examiner respectfully disagrees. Sumitomo states in [col 7 lines 60-63] “ the element gate electrode 25a and the dummy gate electrode 25b in the first gate electrode 17a formed in the IGBT region 1a are controller [sic] independently”. Note that [col 8 lines 7-11] is only an example of how the third pad is configured, not the only configuration…“ For example, the third gate pad 3c is connected to the ground electric potential of the external circuit so that the electric potential of the dummy gate electrode 25b is maintained to be the ground voltage (i.e., 0V).” As is explicitly stated in [col 8 lines 24-26] “the dummy gate electrode 25b is connected to the third gate pad 3c, and the voltage can be applied to the dummy gate electrode 25b independently.” Thus, it does not have to be grounded and can be configured to have a different timing.
The Examiner points to [col 8 lines 26-32] to show that the gate can be controlled independently. “Accordingly, similar to the second embodiment, after the semiconductor device is manufactured (before the semiconductor device is shipped), the voltage higher than a guaranteed voltage can be applied to the dummy gate electrode 25b. Thus, a screening test for the gate insulation film 16 on which the dummy gate electrode 25b is arranged is appropriately performed.” When there is a higher voltage (not ground) that voltage can be applied to the “dummy gate” of the device. Grounding is only an example of a configuration. Thus, there is a control unit, a gate controlled independently and a voltage that can be applied to “dummy gate”. The rejection of claim 1 is upheld.
Regarding the Applicants Remarks on page 8 on the new claim 16, claim 16 is rejected under 35 USC § 112 below. New claim 16 discloses: “a drive timing for the first trench and a drive timing for the second trench are not the same.” However, there is no structural difference disclosed in the body of the claim related to the different drive timings. Claim 16 is a device claim. Drive timings are not a device feature, but a method of using. The Examiner respectfully argues that claim 16 is missing structural limitations that describe how the timings are made.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The new claim 16 discloses “…and a drive timing for the first trench and a drive timing for the second trench are not the same.” The omitted structural cooperative relationships are: structural limitations related to the method of using drive timings.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4 and 11 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sumitomo et al. (US 10388773) herein referred to as Sumitomo.
As to claim(s) 1, and new claim 16, Sumitomo teaches a semiconductor device comprising:
a semiconductor substrate (Fig. 7 substrate 10) of a first conductive type ([col 3 lines 66-67] n-type substrate is of first conductivity type semiconductor substrate 10 having a N− conductive type “ ) having a first region (Fig. 7 IGBT region) and a second region (Fig. 7 diode region 1b) which are adjacent to each other;
a base layer ([col 4 line 7] “p-type base layer 12” ) of a second conductive type formed on an upper surface side of the semiconductor substrate (Fig. 7 substrate 10);
a source layer ([col 4 line 21] ” The emitter region 14 having the N+ conductive type is source”) of the first conductive type formed on an upper surface side of the base layer (Fig. 7, “p-type base layer 12” );
a plurality of gate electrodes (Fig 7, 1st and 2nd gate electrodes 17a and 17b) respectively formed via gate insulator films (col4 line 46 Fig. 7, gate insulating films 16) inside a plurality of trenches ([col 4 line35] Fig. 7, “ trench 13) penetrating the source layer ([col 4 line 21] ” The emitter region 14 having the N+ conductive type is source”) and the base layer ([col 4 line 7] “p-type base layer 12” ) from the upper surface side of the semiconductor substrate (Fig. 7, substrate 10);
an emitter electrode ([col 5 lines 1-2] Fig. 7 ”upper electrode 19” The upper electrode 19 is electrically connected to the emitter region 14 and the body region 15 via the contact hole 18a, 18b in the IGBT region 1a and the diode region 1b, respectively.) formed on the upper surface of the semiconductor substrate (Fig. 7 substrate 10);
a collector layer ([col 5 line 55] “the collector layer 21 having the P conductive type” ) of the second conductive type formed on a lower surface side of the semiconductor substrate (Fig. 1 substrate 10);
a collector electrode ([col 5 line 39-40] “lower electrode 23”) formed on the lower surface of the semiconductor substrate (Fig 7. substrate 10), wherein the trench in the first region (Fig. 7, IGBT region (1a)) includes a first trench (Annotated 1st trench), and two or more second trenches (Annotated 2nd trenches), that sandwich the first trench (Annotated 1st trench), from both sides,
the gate electrodes (Fig 7 gate electrode 17a) formed in the two or more second trenches are connected to each other and are not connected to the gate electrode formed in the first trench (Annotated 1st trench), ([col 7 lines 54-63]“The first gate electrode 17a includes the element gate electrode 25a and a dummy gate electrode 25b. The element gate electrode 25a is electrically connected to the first gate pad 3a via the first gate runner 2a. The dummy gate electrode 25b is electrically connected to the third gate pad 3c via the third gate runner 2c. Thus, the element gate electrode 25a and the dummy gate electrode 25b in the first gate electrode 17a formed in the IGBT region 1a are controller independently.”)
the gate electrode (Fig 7 gate electrode 17b) formed in the trench in the second region (Fig. 7, diode region 1b) is connected to the emitter electrode ([col 5 lines 1-2] Fig. 7 ”upper electrode 19” The upper electrode 19 is electrically connected to the emitter region 14 and the body region 15 via the contact hole 18a, 18b in the IGBT region 1a and the diode region 1b, respectively.), and
the base layer ([col 4 line 7] “p-type base layer 12”) is connected to the emitter electrode in a region between the first region (IGBT region (1a)) and the second region (diode region 1b).
a drive timing for the first trench and a drive timing for the second trench are not the same. (In semiconductor manufacturing and layout design, if you have independent drive timing controls for each trench, the optimal drive timing for the second trench will inherently differ from the first due to physical variations and parasitics. [col 7 lines 60-63] “ the element gate electrode 25a and the dummy gate electrode 25b in the first gate electrode 17a formed in the IGBT region 1a are controller [sic] independently”.
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a control unit configured to turn off the gate electrode in the first trench at a different timing than the gate electrode in the second trench. [col 7 lines 60-63] “ the element gate electrode 25a and the dummy gate electrode 25b in the first gate electrode 17a formed in the IGBT region 1a are controller [sic] independently”
As to claim 2, (Currently Amended) Sumitomo teaches the semiconductor device according to claim 1, as discussed above, and further discloses
wherein the control unit is configured to turn off the gate electrode in a control gate trench at a timing earlier than a timing for the gate electrode in an active trench, [col 7 lines 60-63] “ the element gate electrode 25a and the dummy gate electrode 25b in the first gate electrode 17a formed in the IGBT region 1a are controller [sic] independently”
wherein the control unit (3a,3c) wherein the first trench (Annotated 1st trench) is the active trench ([col 7 lines54-56] “The first gate electrode 17a includes the element gate electrode 25a and a dummy gate electrode 25b.”), and the second trench (Annotated 2nd trench) is the control gate trench (control gate electrode 17b).
Additionally, claim 2 recites the performance properties of the device (i.e. a control unit configured to turn off the gate electrode in a control gate trench at a timing earlier than a timing for the gate electrode in an active trench). This functional limitation does not distinguish the claimed device over the prior art, since it appears that this limitation can be performed by the prior art structure of Sumitomo. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) See MPEP 2114.
As to claim 4, (Currently Amended) Sumitomo teaches the semiconductor device according to claim 1, as discussed above, and further discloses wherein the
control unit (3a,3c) is configured to turn on the gate electrode in a control gate trench at a timing later than a timing for the gate electrode in an active trench, [col 7 lines 60-63] “ the element gate electrode 25a and the dummy gate electrode 25b in the first gate electrode 17a formed in the IGBT region 1a are controller [sic] independently”
the first trench (Annotated 1st trench) is the active trench, and the second trench (Annotated 2nd trench) is the control gate trench ([col 7 lines54-56] The first gate electrode 17a includes the element gate electrode 25a and a dummy gate electrode 25b.).
Additionally, claim 4 recites the performance properties of the device (i.e. a control unit turn
on the gate electrode in a control gate trench at a timing later than a timing for the gate electrode in an active trench.) This functional limitation does not distinguish the claimed device over the prior art, since it appears that this limitation can be performed by the prior art structure of Sumitomo. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) See MPEP 2114.
As to claim(s) 11, Sumitomo teaches the semiconductor device according to claim 1, further comprising
a carrier accumulation layer (drift layer 11) of the first conductive type (n-type substrate is of first conductivity type semiconductor formed below the base layer ([col 4 line 7] “p-type base layer 12”).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumitomo et al. (US 10388773) herein referred to as Sumitomo in view of Sako et al. (US 20210384335), herein referred to as Sako.
As to claim(s) 12, Sumitomo teaches the semiconductor device according to claim 11, wherein
carrier accumulation layer (Fig. 7 drift layer 11, Sumitomo) in the first region (Fig. 7 IGBT region (1a), Sumitomo)
Sumitomo does not appear to expressly disclose "an impurity concentration of the carrier accumulation layer (Fig. 7 drift layer 11, Sumitomo) in the first region (Fig. 7 IGBT region (1a), Sumitomo) is higher (obvious) than an impurity concentration of the carrier accumulation layer in the second region (Fig. 7 diode region (1b) Sumitomo).
Sako teaches in [0054] “Even when the n-type carrier accumulation layer 2 is provided in the IGBT region 10, it is possible to not provide the n-type carrier accumulation layer 2 in the diode region 20” ( i.e. the n-type carrier concentration is higher in the IGBT region than in the diode region.) It is advantageous to have the N-type carrier accumulation layer significantly higher in the IGBT region than in the diode region because the IGBT relies on a positive gate-to-emitter voltage to form an active inversion channel. This structure drives a massive influx of electrons to conduct current, fundamentally altering the carrier concentration.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make an impurity concentration of the Sumitomo carrier accumulation layer in the first region higher than an impurity concentration of the carrier accumulation layer in the second region, such as is in the Sako device, so as to increase the number of electrons to conduct current, increasing the performance of the device.
As to claim(s) 13, the Sumitomo/Sako device teaches the semiconductor device according to claim 4, as discussed above, and further
a carrier accumulation layer (Fig. 7 drift layer 11, Sumitomo) of the first conductive type formed below the base layer ([col 4 line 7] “p-type base layer 12”, Sumitomo), wherein
an impurity concentration of the carrier accumulation layer (Fig. 7 drift layer 11, Sumitomo) in contact with the control gate trench (Annotated 2nd trench, Sumitomo) is higher than an impurity concentration of the carrier accumulation layer (Fig. 7 drift layer 11, Sumitomo) in contact with the active trench (Annotated 1st trench, Sumitomo).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumitomo et al. (US 10388773) herein referred to as Sumitomo in view of Konishi et al. (US 20180204909), herein referred to as Konishi.
As to claim(s) 15, Sumitomo discloses the elements of claim 1 as discussed above. However,
Sumitomo does not appear to expressly disclose “the semiconductor substrate is made of a wide-band-gap semiconductor (obvious). “
Konishi teaches in ([0064] “The semiconductor substrate 10 may be made of silicon, or may be made of a wide bandgap semiconductor…“) Wide bandgap materials, such as Gallium Nitride (GaN) and Silicon Carbide (SiC), offer superior performance over conventional silicon by enabling higher efficiency, faster switching speeds, and higher temperature tolerance. These materials allow for smaller, lighter, and more reliable power electronics, crucial for semiconductor devices. It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the semiconductor substrate of the Sumitomo device of a wide-band-gap semiconductor, such as is in the Konishi device, so as to have lower energy losses, resulting in higher efficiency in power conversion.
Allowable Subject Matter
Claim(s) 3, 5-10, and 14 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art taken either singularly or in combination, fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims. The closest prior art is Sumitomo et al. (US 10388773) herein referred to as Sumitomo which teaches analogous devices.
As to claim(s) 3, Sumitomo teaches the semiconductor device according to claim 2, as discussed above. Sumitomo teaches a number of control gate trenches (Annotated 2nd trench) and a number of active trenches (Annotated 1st trench) in the first region (IGBT region).
Sumitomo does not teach:
“the number of the control gate trenches is three times or more of the number of the active trenches in the first region.”
As to claim(s) 5, (Currently Amended) Sumitomo teaches the semiconductor device according to claim 1, as discussed above. Sumitomo teaches a control unit (3a,3c), a first trench (Annotated 1st trench) and a second trench (Annotated 1st trench) and the control unit is configured to turn off the gate electrode in a control gate trench at a timing earlier than a timing for the gate electrode in an active trench [col 7 lines 60-63] “ the element gate electrode 25a and the dummy gate electrode 25b in the first gate electrode 17a formed in the IGBT region 1a are controller [sic] independently”.
Sumitomo does not teach:
“a control unit wherein the first trench is the control gate trench, and the second trench is the active trench. “
As to claim(s) 6, Sumitomo teaches the semiconductor device according to claim 5, as discussed above. Sumitomo teaches active trenches (Annotated 1st trench), control gate trenches (Annotated 2nd trench) and a first region (IGBT region).
Sumitomo does not teach:
“the number of the active trenches is three times or more of the number of the control gate trenches in the first region”
As to claim(s) 7, Sumitomo teaches the semiconductor device according to claim 2, as discussed above. Sumitomo teaches the semiconductor substrate (Fig. 7 substrate 10) has a third region (any region other than the 1st and 2nd region).
Sumitomo does not teach:
“the second region is positioned between the first region and the third region”
Sumitomo teaches a control gate trench (Annotated 2nd trench) and an active trench (Annotated 1st trench).
Sumitomo does not teach:
“the control gate trench and two or more active trenches that sandwich the control gate trench from both sides are formed in the third region”.
As to claim(s) 8, Sumitomo teaches the semiconductor device according to claim 2, as discussed above. Sumitomo teaches the semiconductor substrate (Fig. 7 substrate 10) has a third region (any region other than the 1st and 2nd region), the first region (Fig. 7, IGBT region (1a)), the second region (Fig. 7, diode region (1b)), and active trenches (Annotated 1st trench),
Sumitomo does not teach:
“the semiconductor substrate has a third region, the second region is positioned between the first region and the third region”, and
“a ratio of the active trenches in the trenches formed in the third region is larger than a ratio of the active trenches in the trenches formed in the first region”.
As to claim(s) 9, Sumitomo teaches the semiconductor device according to claim 2, as discussed above. Sumitomo teaches the semiconductor substrate (Fig. 7 substrate 10) has a third region (any region other than the 1st and 2nd region), a second region (Fig. 7 diode region 1b), the first region (IGBT region) and one or more control gate (Annotated 2nd trench).
Sumitomo does not teach:
“the semiconductor substrate has a third region, the second region is positioned between the first region and the third region,” and
“one or more control gate trenches are formed in the third region”.
As to claim(s) 10, Sumitomo teaches the semiconductor device according to claim 1, as discussed above. Sumitomo teaches the second region (Fig. 7 diode region 1b) and the first region (IGBT region).
Sumitomo does not teach:
the number of the trenches included in the second region (Fig. 7 diode region 1b) is equal to or larger than the number of the trenches included in the first region (IGBT region).
As to claim(s) 14, Sumitomo teaches the semiconductor device according to claim 1, as discussed above wherein
Sumitomo does not teach:
the semiconductor device is an RC-IGBT.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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