DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 10-15 in the reply filed on Jun. 23rd 2026 is acknowledged. Claims 10-15 and 24-27 are examined in this office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20100044850) in view of Caparas et al. (US 20100001385 from IDS).
Regarding claim 10, Lin teaches a method (Abstract) of manufacturing a hybrid Quad Flat No-Lead (QFN) (non-lead-type (QFN) packages; para. 0005) and Quad Flat Package (QFP) (quad flat package (QFP); para. 0005) integrated circuit package, comprising:
forming in an upper surface of a base plate (fig. 3D, upper surface of carrier 200; para. 0033), a first die pad opening (left cavity 220a; para. 0047), a second die pad opening (right 220a), and recesses (recess first openings S1; para. 0047) surrounding pad structures (inner leads 232; para. 0047) positioned between the first and second die pad openings (two 220a);
mounting a first integrated circuit (fig. 3D, left chip 300; para. 0048) at the first die pad opening (left 220a);
mounting a second integrated circuit (right 300) at the second die pad opening (right 220a);
encapsulating (fig. 3G, molding compound 500; para. 0050) the base plate (200), the first integrated circuit (left 300) mounted at the first die pad opening (left 220a), the second integrated circuit (right 300) mounted at the second die pad opening (right 220a);
thinning the base plate (fig. 3H(b) thinning 200, at least portion 200) from a backside (bottom side) thereof to remove material of the base plate (remove material of portion 200) until reaching the recesses (S1) surrounding pad structures (232) and producing a plurality of QFN conductive pads (232 for QFN package; para. 0003).
Lin fails to teach processing a metal plate to provide a proto-leadframe structure that includes the base plate and a plurality of lead structures;
encapsulating proximal ends of the plurality of lead structures;
processing distal ends of the lead structures to produce a plurality of QFP conductive leads.
However, Caparas teaches processing a metal plate (Caparas: fig. 14, lead frame 1302; para. 0123) to provide a proto-leadframe structure (Caparas: proto lead frame of 1302) that includes the base plate (Caparas: paddle 1372; para. 0123, similar to 200 of Lin) and a plurality of lead structures (Caparas: external connectors 1368; para. 0123);
encapsulating (Caparas: fig. 23, encapsulation 102; para. 0047) proximal ends of the plurality of lead structures (Caparas: proximal ends of 1368);
processing distal ends of the lead structures (Caparas: fig. 26, bent distal ends of 1368 as External interconnects 510; para. 0072) to produce a plurality of QFP conductive leads (Caparas: leads for external connect for QFP package).
Caparas and Lin are considered to be analogous to the claimed invention because they are in the same field of package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add Quad Flat Package (QFP) integrated circuit package with lead structures as taught by Caparas.
Doing so would realize lead structures for QFP with more external I/O to reduce manufacturing costs (Caparas: para. 0009).
Regarding claim 11, Lin in view of Caparas teaches the method of claim 10 including the plurality of lead structures (Caparas: fig. 14, 1368).
Lin in view of Caparas according to claim 10 fails to explicitly teach applying a solder layer to upper surfaces of the pad structures; and
wirebonding one or more of the first and second integrated circuits to the solder layer at the upper surfaces of the pad structures.
However, Caparas teaches applying a solder layer (Caparas: fig. 26, soldering the external leads; para. 0005) to upper surfaces of the plurality of lead structures (Caparas: upper surfaces of 1368 for wiring) at the proximal ends (Caparas: proximal ends of 1368) thereof; and
wirebonding (Caparas: internal interconnects 242 with bond wires; para. 0055) one or more of the first and second integrated circuits (Caparas: first integrated circuit 214; para. 0055, similar to 300 of Lin) to the solder layer at the proximal ends of the plurality of lead structures (Caparas: soldering on 1368).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add solder layer for wirebonding as taught by Caparas.
Doing so would realize wirebonding for lead structures for QFP with more external I/O to reduce manufacturing costs (Caparas: para. 0009).
Regarding claim 12, Lin in view of Caparas further teaches the method of claim 10, further comprising:
applying a solder layer (Lin: fig. 3F, first patterned metal layer 218a for wiring; para. 0046 and Caparas: soldering contact pad) to upper surfaces of the pad structures (Lin: upper surfaces of 232); and
wirebonding (Lin: wires 400; para. 0037) one or more of the first and second integrated circuits (Lin: 300) to the solder layer at the upper surfaces of the pad structures (Lin: 218a on 232).
Regarding claim 13, Lin in view of Caparas further teaches the method of claim 10, further comprising:
applying a solder layer (Lin: fig. 3E, adhesive layer 600) to bottoms of the first and second die pad openings (Lin: bottoms of two 220a); and
wherein mounting the first and second integrated circuits (Lin: two 300) comprises mounting to the solder layer (Lin: 600).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Caparas as applied to claim 10 above, and further in view of Camacho et al. (US 20120139104).
Regarding claim 14, Lin in view of Caparas further teaches the method of claim 10, further comprising, after forming the recesses (Lin: fig. 3F, S1) surrounding pad structures (Lin: 232) and
Lin in view of Caparas fails to teach before encapsulating the base plate, applying an insulating layer to bottoms of the recesses surrounding pad structures.
However, Camacho teaches before encapsulating (Camacho: fig. 8, 9, before encapsulation 152) the base plate (Camacho: leadframe 302; para. 0072, similar to 200 of Lin), applying an insulating layer (Camacho: passivation 118; para. 0038) to bottoms of the recesses (Camacho: bottoms of recess for 118) surrounding pad structures (Camacho: outer pad 126; para. 0043, similar to 232 of Lin).
Camacho, Caparas and Lin are considered to be analogous to the claimed invention because they are in the same field of package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an insulating layer as taught by Camacho.
Doing so would realize a passivation layer to improve reliability by isolating the interconnect structure (Camacho: para. 0062).
Regarding claim 15, Lin in view of Caparas and Camacho teaches the method of claim 14 including thinning the base plate (Lin: fig. 3H(b) thinning 200, at least portion 200).
Lin in view of Caparas and Camacho according to claim 14 fails to explicitly teach thinning the base plate is continued until the insulating layer at the bottoms of the recesses surrounding pad structures is reached.
However, Camacho teaches thinning the base plate (Camacho: fig. 10, thinning 302, at least portion 302, similar to 200 of Lin) is continued until the insulating layer (Camacho: 118) at the bottoms of the recesses (Camacho: bottoms of recess for 118) surrounding pad structures (Camacho: 126) is reached.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add thinning the base plate is continued until the insulating layer as taught by Camacho.
Doing so would realize keeping the passivation layer to improve reliability by isolating the interconnect structure (Camacho: para. 0062).
Claims 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over in Lin in view of Caparas and Camacho.
Regarding claim 24, Lin teaches a method (Abstract) of manufacturing a hybrid Quad Flat No-Lead (QFN) (non-lead-type (QFN) packages; para. 0005) and Quad Flat Package (QFP) (quad flat package (QFP); para. 0005) integrated circuit package, comprising:
forming in an upper surface of a base plate (fig. 3D, upper surface of carrier 200; para. 0033), a first die pad opening (left cavity 220a; para. 0047), a second die pad opening (right 220a), and recesses (recess first openings S1; para. 0047) surrounding pad structures (inner leads 232; para. 0047) positioned between the first and second die pad openings (two 220a), said recesses (fig. 1C, S1) having a depth (depth of molding compound 500, which to the bottom of S1; para. 0050) greater than depths of the first and second die pad openings (depth of 220a);
mounting a first integrated circuit (fig. 3D, left chip 300; para. 0048) at the first die pad opening (left 220a);
mounting a second integrated circuit (right 300) at the second die pad opening (right 220a);
forming an encapsulation (fig. 3G, molding compound 500; para. 0050) that covers the upper surface of the base plate (upper surface of 200), fills the recesses (S1), encapsulates the first integrated circuit (left 300), encapsulates the second integrated circuit (right 300);
thinning the base plate (fig. 3H(b) thinning 200, at least portion 200) from a backside (bottom side) thereof to remove material of the base plate (remove material of portion 200), wherein thinning defines (separate define) from the pad structures (232) of the base plate (200) a plurality of QFN conductive pads (232 for QFN package; para. 0003) surrounded by the recesses (S1).
Lin fails to teach processing a metal plate to provide a proto-leadframe structure that includes the base plate and a plurality of lead structures;
encapsulating proximal ends of the plurality of lead structures;
processing distal ends of the lead structures to produce a plurality of QFP conductive leads.
However, Caparas teaches processing a metal plate (Caparas: fig. 14, lead frame 1302; para. 0123) to provide a proto-leadframe structure (Caparas: proto lead frame of 1302) that includes the base plate (Caparas: paddle 1372; para. 0123, similar to 200 of Lin) and a plurality of lead structures (Caparas: external connectors 1368; para. 0123);
encapsulating (Caparas: fig. 23, encapsulation 102; para. 0047) proximal ends of the plurality of lead structures (Caparas: proximal ends of 1368);
processing distal ends of the lead structures (Caparas: fig. 26, bent distal ends of 1368 as External interconnects 510; para. 0072) to produce a plurality of QFP conductive leads (Caparas: leads for external connect for QFP package).
Caparas and Lin are considered to be analogous to the claimed invention because they are in the same field of package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add Quad Flat Package (QFP) integrated circuit package with lead structures as taught by Caparas.
Doing so would realize lead structures for QFP with more external I/O to reduce manufacturing costs (Caparas: para. 0009).
In addition, Lin in view of Caparas fails to teach applying an insulating layer at a bottom of each of the recesses;
thinning at least until reaching the insulating layer applied at bottoms of the recesses.
However, Camacho teaches applying an insulating layer (Camacho: fig. 8 passivation 118; para. 0038) at a bottom of each of the recesses (Camacho: bottoms of recess for 118, similar to S1 of Lin);
thinning (Camacho: fig. 10, thinning 302, at least portion 302) at least until reaching the insulating layer (Camacho: 118) applied at bottoms of the recesses (Camacho: bottoms of recess for 118).
Camacho, Caparas and Lin are considered to be analogous to the claimed invention because they are in the same field of package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an insulating layer as taught by Camacho.
Doing so would realize a passivation layer to improve reliability by isolating the interconnect structure (Camacho: para. 0062).
Regarding claim 25, Lin in view of Caparas and Camacho teaches the method of claim 24 including the plurality of lead structures (Caparas: fig. 14, 1368).
Lin in view of Caparas and Camacho according to claim 24 fails to explicitly teach applying a solder layer to upper surfaces of the pad structures; and
wirebonding one or more of the first and second integrated circuits to the solder layer at the upper surfaces of the pad structures; wherein forming the encapsulation also encapsulates the wirebonding.
However, Caparas teaches applying a solder layer (Caparas: fig. 2, soldering the external leads; para. 0005) to upper surfaces of the plurality of lead structures (Caparas: upper surfaces of 1368 for wiring) at the proximal ends (Caparas: proximal ends of 1368) thereof; and
wirebonding (Caparas: internal interconnects 242 with bond wires; para. 0055) one or more of the first and second integrated circuits (Caparas: first integrated circuit 214; para. 0055, similar to 300 of Lin) to the solder layer at the proximal ends of the plurality of lead structures (Caparas: soldering on 1368);
wherein forming the encapsulation (Caparas: 102) also encapsulates the wirebonding (Caparas: 242).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add solder layer with wirebonding as taught by Caparas.
Doing so would realize the wirebonding for lead structures for QFP with more external I/O to reduce manufacturing costs (Caparas: para. 0009).
Regarding claim 26, Lin in view of Caparas and Camacho teaches the method of claim 24, further comprising:
wirebonding (Lin: fig. 3F, wires 400; para. 0037) one or more of the first and second integrated circuits (Lin: 300) to the upper surfaces of the pad structures (Lin: 218a on 232);
wherein forming the encapsulation (Lin: 500) also encapsulates the wirebonding (Lin: 400).
Lin in view of Caparas and Camacho according to claim 24 fails to explicitly teach applying a solder layer to upper surfaces of the pad structures;
wirebonding to the solder layer.
However, Caparas teaches applying a solder layer (Caparas: fig. 2, soldering the contact pads; para. 0005) to upper surfaces of the pad structures (Caparas: first extension 218; para. 0050, similar to 232 of Lin);
wirebonding (Caparas: internal interconnects 236 with bond wires; para. 0055) to the solder layer (Caparas: soldering on contact pads).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a solder layer as taught by Caparas.
Doing so would realize a solder layer to improve power and signal connections (Caparas: para. 0005).
Regarding claim 27, Lin in view of Caparas and Camacho teaches the method of claim 24 including the first and second die pad openings (Lin: fig. 3E, bottoms of two 220a).
Lin in view of Caparas and Camacho according to claim 24 fails to explicitly teach applying a solder layer at bottoms of the first and second die pad openings; and
wherein mounting the first and second integrated circuits comprises mounting to the solder layer.
However, Camacho teaches applying a solder layer (Camacho: fig. 1, internal connector 150 including solder; para. 0097) at bottoms of the first and second die pad openings (Camacho: bottom for die 144, similar to 220a for chip 300 of Lin); and
wherein mounting the first and second integrated circuits (Camacho: 144, similar to 300 of Lin) comprises mounting to the solder layer (Camacho: 150).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a solder layer as taught by Camacho.
Doing so would realize a solder layer to improve conductive connectors (Camacho: para. 0097).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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