Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 5, 6, 10 and 21 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sung (KR 20190125887, machine-translation provided).
Regarding Claim 1
FIG. 4 of Sung discloses a semiconductor package, comprising: a first die (100, FIG. 8) having a signal region (center) and a dummy region (sides) that surrounds the signal region in a plan view of the semiconductor package; and a second die (FIG. 8) stacked on the first die, wherein the first die includes: a plurality of first dummy patterns (377) arranged in a first direction on the dummy region; a plurality of second dummy patterns (375) on the dummy region and arranged in the first direction between the first dummy patterns; a first dielectric layer (500 on 10-1) on the first dummy patterns and the second dummy patterns; and a plurality of first pads (400) that extend through the first dielectric layer and are coupled to the first dummy patterns (FIG. 2), wherein the second die includes: a plurality of second pads (FIG. 8) on the dummy region at positions that correspond to positions of the first dummy patterns; and a plurality of third pads on the dummy region at positions that correspond to positions of the second dummy patterns, wherein the first dielectric layer is between the second dummy patterns and the third pads, wherein on an interface between the first die and the second die, the first pads contact the second pads (FIG. 8), and wherein the first dummy patterns are connected to a ground circuit or a power circuit of the first die (text: the first extension line 320 may constitute a path for providing power or ground).
Regarding Claim 5
FIG. 8 of Sung discloses the first die further includes a plurality of fourth pads that extend through the first dielectric layer and are coupled to the second dummy patterns, wherein the first dielectric layer is between the third pads and the fourth pads.
Regarding Claim 6
FIG. 8 of Sung discloses the first die further includes a plurality of fourth pads on the second dummy patterns, wherein, on the interface between the first die and the second die, the fourth pads are in contact with the third pads, and wherein the first dielectric layer is between the second dummy patterns and the fourth pads.
Regarding Claim 10
FIG. 8 of Sung discloses the second die further includes a second dielectric layer that surrounds the second pads and the third pads in the plan view of the semiconductor package, wherein, on the interface between the first die and the second die, the first dielectric layer and the second dielectric layer are in contact with each other.
Regarding Claim 21
FIG. 4 of Sung discloses a semiconductor package, comprising: a substrate (204); a first die (100, FIG. 8) having a signal region (center) and a dummy region (sides) that surrounds the signal region in a plan view of the semiconductor package; and a second die (FIG. 8) stacked on the first die; and a molding layer (500) on the substrate and surrounding the first die and the second die in the plan view of the semiconductor package, wherein the first die includes: a plurality of first dummy patterns (377) and a plurality of second dummy patterns (375) that are alternately arranged in a first direction on the dummy region; a first dielectric layer (500 on 10-1) on the first dummy patterns and the second dummy patterns; and a plurality of first pads (400) that are arranged to constitute at least one row that extends along a second direction on the first dummy patterns, the second direction intersecting the first direction; and a plurality of second pads that are arranged to constitute one row that extends along the second direction on the second dummy patterns, wherein the second die includes: a plurality of third pads on the dummy region at positions that correspond to positions of the first pads; and a plurality of fourth pads at positions that correspond to positions of the second pads, wherein the first pads are in contact with the second pads and the first dummy patterns, wherein the first dielectric layer is between the fourth pads and the second pads or between the second pads and the second dummy patterns (FIG. 8), and wherein the first dummy patterns are connected to a ground circuit or a power circuit of the first die (text: the first extension line 320 may constitute a path for providing power or ground).
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 rejected under 35 U.S.C. 103 as being unpatentable over Sung, in view of Kim (KR 20220027535, machine-translation provided).
Regarding Claim 2
Sung disclose Claim 1, wherein the first dummy patterns are connected to the power circuit of the first die.
Sung is silent with respect to “the second dummy patterns are connected to the ground circuit of the first die”.
FIG. 28 of Kim discloses a similar semiconductor package, wherein the second dummy patterns (314) are connected to the ground circuit of the first die (text: The third dummy pattern 314 may be provided integrally with the third ground pattern 312b).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Kim. The ordinary artisan would have been motivated to modify Sung in the above manner for purpose of preventing bending phenomenon (text of Kim).
Regarding Claim 3
FIG. 28 of Kim discloses when viewed in the first direction, a width of the first dummy patterns (314) is greater than a width of the second dummy patterns (324).
Regarding Claim 4
Sung as modified by Kim discloses the first dummy patterns are connected to the ground circuit of the first die, and the second dummy patterns are connected to the power circuit of the first die.
Claim 7 rejected under 35 U.S.C. 103 as being unpatentable over Sung, in view of Tomita (U.S. Patent Pub. No. 2008/0283961).
Regarding Claim 7
Sung disclose Claim 1.
Sung is silent with respect to “when viewed in the first direction, a pitch between neighboring first pads is in a range of about 3 micrometers to about 30 micrometers”.
FIG. 1 of Tomita discloses a similar semiconductor package, wherein when viewed in the first direction, a pitch between neighboring first pads is in a range of about 3 micrometers to about 30 micrometers [0064].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Tomita. The ordinary artisan would have been motivated to modify Sung in the above manner, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Claims 8, 11 and 14-17 rejected under 35 U.S.C. 103 as being unpatentable over Sung, in view of Sano (JP 2008066716, machine-translation provided).
Regarding Claim 8
Sung disclose Claim 1.
Sung is silent with respect to “in the first die, two of the first dummy patterns and one of the second dummy patterns are alternately arranged in the first direction”.
FIG. 8 of Sano discloses a similar semiconductor package, wherein in the first die, two of the first dummy patterns (8) and one of the second dummy patterns (7) are alternately arranged in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Sano. The ordinary artisan would have been motivated to modify Sung in the above manner for purpose of improving the mechanical strength (text of Sano).
Regarding Claim 11
FIG. 4 of Sung discloses a semiconductor package, comprising: a first die (100, FIG. 8) having a signal region (center) and a dummy region (sides) that surrounds the signal region in a plan view of the semiconductor package; and a second die (FIG. 8) stacked on the first die, wherein the first die includes: a plurality of first dummy patterns (377) and a plurality of second dummy patterns (375) that extend in a first direction on the dummy region; a first dielectric layer (500 on 10-1) on the first dummy patterns and the second dummy patterns; a plurality of first pads (400) on the first dummy patterns; and a plurality of second pads on the second dummy patterns the second dummy patterns (FIG. 2), wherein the second die includes: a plurality of third pads (FIG. 8) on the dummy region at positions that correspond to positions of the first dummy patterns; and a plurality of third pads on the dummy region at positions that correspond to positions of first pads; and a plurality of fourth pads at positions that correspond to positions of the second pads, wherein the third pads are electrically connected through the first pads to the first dummy patterns, and wherein the fourth pads are electrically insulated from the second dummy patterns (FIG. 8).
Sung is silent with respect to the first dummy patterns and the second dummy patterns “are alternately arranged in a second direction that intersects the first direction”.
FIG. 8 of Sano discloses a similar semiconductor package, wherein the first dummy patterns (8) and the second dummy patterns (7) are alternately arranged in a second direction that intersects the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Sano. The ordinary artisan would have been motivated to modify Sung in the above manner for purpose of improving the mechanical strength (text of Sano).
Regarding Claim 14
FIG. 8 of Sung discloses the first dielectric layer is between the fourth pads and the second pads, and the second pads are connected to the second dummy patterns.
Regarding Claim 15
FIG. 8 of Sung discloses the first dielectric layer is between the second pads and the second dummy patterns, and on an interface between the first die and the second die, the second pads are in direct contact with the fourth pads.
Regarding Claim 16
FIG. 8 of Sung discloses on an interface between the first die and the second die, the first pads are in direct contact with the third pads.
Regarding Claim 17
FIG. 30 of Sano discloses on one of the first dummy patterns, the first pads are arranged to constitute at least two rows that extend along the first direction, and on one of the second dummy patterns, the second pads are arranged to constitute one row that extends along the first direction.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Sung, in view of Lai (U.S. Patent Pub. No. 2011/0278739).
Regarding Claim 9
Sung disclose Claim 1.
Sung is silent with respect to “the first die further includes: a peripheral region between the signal region and the dummy region; and a plurality of first power pads and a plurality of first ground pads on the peripheral region, wherein the second die further includes a plurality of second power pads and a plurality of second ground pads on the peripheral region, wherein the first power pads are electrically connected to the power circuit of the first die, wherein the first ground pads are electrically connected to the ground circuit of the first die, and wherein, on the interface between the first die and the second die, the first power pads are in contact with the second power pads, and the first ground pads are in contact with the second ground pads”.
FIG. 2 of Lai discloses a similar semiconductor package, wherein the first die further includes: a peripheral region between the signal region and the dummy region; and a plurality of first power pads (225) and a plurality of first ground pads (228) on the peripheral region, wherein the second die further includes a plurality of second power pads (221) a plurality of second ground pads (26) on the peripheral region, wherein the first power pads are electrically connected to the power circuit of the first die, wherein the first ground pads are electrically connected to the ground circuit of the first die, and wherein, on the interface between the first die and the second die, the first power pads are in contact with the second power pads, and the first ground pads are in contact with the second ground pads.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Lai. The ordinary artisan would have been motivated to modify Sung in the above manner for purpose of reducing the package thickness and manufacturing cost ([0005] of Lai).
Claims 12 and 13 rejected under 35 U.S.C. 103 as being unpatentable over Sung and Sano, in view of Kim (KR 20220027535, machine-translation provided).
Regarding Claim 12
Sung as modified by Sano disclose Claim 1, wherein the first dummy patterns are connected to a power circuit of the first die.
Sung as modified by Sano is silent with respect to “the second dummy patterns are connected to a ground circuit of the first die”.
FIG. 28 of Kim discloses a similar semiconductor package, wherein the second dummy patterns (314) are connected to a ground circuit of the first die (text: The third dummy pattern 314 may be provided integrally with the third ground pattern 312b).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Kim. The ordinary artisan would have been motivated to modify Sung in the above manner for purpose of preventing bending phenomenon (text of Kim).
Regarding Claim 13
Sung as modified by Sano and Kim discloses the first dummy patterns are connected to a ground circuit of the first die, and the second dummy patterns are connected to a power circuit of the first die.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Sung and Sano, in view of Kim.
Regarding Claim 18
Sung as modified by Sano disclose Claim 11.
Sung as modified by Sano is silent with respect to “when viewed in the second direction, a width of the first dummy patterns is greater than a width of the second dummy patterns”.
FIG. 28 of Kim discloses a similar semiconductor package, wherein when viewed in the second direction, a width of the first dummy patterns (314) is greater than a width of the second dummy patterns (324).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Kim. The ordinary artisan would have been motivated to modify Sung in the above manner for purpose of preventing bending phenomenon (text of Kim).
Claim 19 rejected under 35 U.S.C. 103 as being unpatentable over Sung and Sano, in view of Tomita.
Regarding Claim 19
Sung as modified by Sano disclose Claim 11.
Sung as modified by Sano is silent with respect to “when viewed in the second direction, a pitch between neighboring first pads is in a range of about 3 micrometers to about 30 micrometers”.
FIG. 1 of Tomita discloses a similar semiconductor package, wherein when viewed in the first direction, a pitch between neighboring first pads is in a range of about 3 micrometers to about 30 micrometers [0064].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sung, as taught by Tomita. The ordinary artisan would have been motivated to modify Sung in the above manner, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Pertinent Art
U.S. Patent Pub. No. 2016/0050744, 2021/0296615; U.S. Patent No. 9,793,246; EP 3173910.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897