DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgment has been made to the amendment received on 07/01/2026. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (CN10938026B) in view of Chiang et al (US20190096929A1).
Re claim 1 Li teaches, an image sensor, comprising:
a substrate (100, fig 1) [page 3, line 53] that comprises a first surface (100b, fig 1) [page
3, line 57] and a second surface (100a, fig 1) [page 3, line 55] that are opposite to each other (see
fig 1), wherein the substrate comprises a plurality of pixel areas (102, fig 1) [page 3, line 59];
an isolation pattern (108/106, fig 1) [page 4, lines 3, 5] that extends from the first surface
(100b) and into the substrate (100, fig 1), wherein the isolation pattern (108/106, fig 1) is between
the plurality of pixel areas (102, fig 1); and
an antireflection layer (128, fig 1) [page 5, line 47] on the isolation pattern (108/106),
wherein the isolation pattern (108/106) comprises:
a first device isolation pattern (108, fig 1) [page 5, line 8] that contacts the antireflection
layer (128, fig 1) [page 5, line 47]; and
a second device isolation pattern (106, fig 1) [page 4, line 8] that is spaced apart from the
antireflection layer (128, fig 1) [page 5, line 47],
wherein the first device isolation pattern (108, fig 1) comprises:
a first dielectric layer (116, fig 1) [page 5, line 17]; and
a conductive reflection layer (114, fig 1) [page 5, line 17] on the first dielectric layer (116,
fig 1), and
wherein a top surface (top of 114) of the conductive reflection layer (114) and a top surface
(116, fig 1) of the first dielectric layer (116) extend from the second surface (110a, fig 1) of the
substrate (100, fig 1) by a same distance (see fig below).
wherein the first device isolation pattern (108, fig 1) is in an extension trench (322, fig 1) [page 4, line 39] and
wherein the second device isolation pattern (106, fig 1) [page 5, line is in a deep trench (Abstract) [page 1, lines 11-37] separated from the antireflection layer (128, fig 1) by the extension trench (306, fig 2) [page 4, line 35].
Li does not teach the extension trench comprises a curved portion, and the curved portion is between the first device isolation pattern and the second device isolation pattern,
Chiang teaches the extension trench (802, fig 8) [0033] comprises a curved portion (see fig 8), and the curved portion is between the first device isolation pattern (BDTI, fig 1) and the second device isolation pattern (110, fig 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chiang into the structure of Li to include the extension trench comprises a curved portion, and the curved portion is between the first device isolation pattern and the second device isolation pattern as claimed.
The ordinary artisan would have been motivated to modify by Li based on the teaching of Chiang in the above manner doing so the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved [0016].
Furthermore, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re claim 7 Li in view of Chiang teaches the image sensor of claim 1, wherein the conductive reflection layer (114, fig 1) comprises at least one of Cu, AL, W (tungsten layer) [Li, page 4 line 30].
Claims 3-4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Li modified by Chiang as applied to claim 1 and further in view of Velichko et al (US 20170229496 A1).
Re claim 3 Li in view of Chiang teaches the image sensor of claim 1, wherein the second device isolation pattern (106, fig 1) comprises:
a buried layer (110, fig 1);
a dielectric liner (112, fig 1) on the conductive liner.
Li and Chiang do not teach a conductive liner on the buried layer; and
the dielectric on the conductive liner.
Velichko does teach a conductive liner (124, fig 7) [0025] on the buried layer (136, fig 7) [0031]; and the dielectric liner (122, fig 7) [0025] on the conductive liner.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Velichko into the structure of Li and Chiang to include a conductive liner on the buried layer; and the dielectric on the conductive liner a conductive liner on the buried layer; and the dielectric on the conductive liner as claimed.
The ordinary artisan would have been motivated to modify Li and Chiang based on the teaching of Velichko in the above manner for the purpose of improving the performance of pixel [0028].
Re claim 4 Li and Chiang in view of Velichko teach the image sensor of claim 3, wherein
a lattice constant of the first dielectric layer (116 A1203, fig 1) [Li page 5, line 17] is different from a lattice constant of the dielectric liner (112-Si3N4). (based on similar materials in the application)
Re claim 6 Li in view of and Chiang and Velichko teach the image sensor of claim 3, wherein the dielectric liner (112-Si3N4) [Li, page 5, line 11] and the first dielectric layer (116 A1203, fig 1) [Li, page 5, line 17] comprise different materials.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Li modified by Chiang and Velichko as applied to claims 1 and 3 further in view of Yun Lee et al (US20160204143A1).
Re claim 5 Li in view of and Chiang and Velichko teach the image sensor of claim 3.
Li, Chiang, and Velichko do not teach a top surface of the dielectric liner comprises a curved surface.
Yun Lee does teach a top surface (top of IL in region 203) [0066] of the dielectric liner (IL, fig 3D) [0066] comprises a curved surface. (see fig 3D).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yun Lee into the structure of Li, Chiang and Velichko to include a top surface of the dielectric liner comprises a curved surface as claimed.
The ordinary artisan would have been motivated to modify Li, Chiang and Velichko based on the teaching of Yun Lee in the above manner so the crosstalk between the pixel regions may be more reduced or prevented [0070].
Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Li and Chiang in view of Kuo et al (US 20190165026A1).
Re claim 8 Li and Chiang teach the image sensor of claim 1, wherein: the antireflection layer (128, fig 1) comprises a parallel layer portion (lateral portion of 128, fig 1) and a vertical layer portion (vertical portion of 128, fig 1) the top surface of the conductive reflection layer (114, fig 1) contacts a bottom surface of the parallel layer portion (114 contact bottom of 128).
Li and Chiang do not teach the vertical layer portion is at least partially surrounded by the conductive reflection layer.
Kuo does teach the vertical layer portion (vertical portion of 304, fig 3) [0036] is at least partially surrounded by the conductive reflection layer (136, fig 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kuo into the structure of Li and Chiang to include the vertical layer portion is at least partially surrounded by the conductive reflection layer as claimed.
The ordinary artisan would have been motivated to modify Li and Chiang based on the teaching of Kuo in the above manner for the purpose of improving quantum efficiency (QE) and modulation transfer function of the image sensor [0016].
Further, it has been held that rearranging part of an invention involves only routine skill in the art, In re Japikse, 86 USPQ 70.
Re claim 9 Li in view of Chiang and Kuo teaches the image sensor of claim 8.
Li does not teach a bottom surface of the vertical portion extends from the second surface of the substrate by a first distance, a bottom surface of the conductive reflection lay er extends from the second surface of the substrate by a second distance, and the first distance is greater than the second distance.
Kuo does teach a bottom surface of the vertical portion (bottom surface of vertical portion of 304, fig 3) [0059] extends from the second surface of the substrate (top 102) [0019] by a first distance (vertical distance of 304), bottom surface of the conductive reflection layer (bottom of 136 in the trench, fig 3) [0026] extends from the second surface (top of 102) [0019] of the substrate by a second distance (vertical distance of 136), and the first distance is greater than the second distance (vertical distance of 304 is greater than vertical distance of 136, see fig 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kuo into the structure of Li and Chiang to include a bottom surface of the vertical portion extends from the second surface of the substrate by a first distance, a bottom surface of the conductive reflection layer extends from the second surface of the substrate by a second distance, and the first distance is greater than the second distance as claimed.
The ordinary artisan would have been motivated to modify Li and Chiang based on the teaching of Kuo in the above manner for the purpose of improving quantum efficiency (QE) and modulation transfer function of the image sensor [0016].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al (CN10938026B) in view of Yoon et al (US20150372031A1).
Re claim 10 Li teaches an image sensor, comprising:
a substrate (100, fig 1) [page 5, line 6] that comprises a first surface (110b, fig 1) [page 5 line 15] and a second surface (110a, fig 1) [page 5 line 15] that are opposite to each other (see fig 1),
wherein the substrate (100, fig 1) [page 5line 6] comprises a plurality of pixel areas (102, fig 1) [page 5, line 6];
an isolation pattern (108/106, fig 1) [page 5, line 8] that extends from the first surface (100a) and into the substrate (100, fig 1),
wherein the isolation pattern (108/106, fig 1) is between the plurality of pixel areas (102, fig 1); and
an antireflection layer (128, fig 1) [page 5 line 47] on the isolation pattern (108/106, fig 1), wherein the isolation pattern comprises:
a first device isolation pattern (108, fig 1) that contacts the antireflection layer (128); and
a second device isolation pattern (106, fig 1) that is spaced apart from the antireflection layer (128, fig 1) [page 5, line 47].
wherein the first device isolation pattern (108, fig 1) [page 5, line 6] comprises:
a first dielectric layer (116, fig 1); and
a conductive reflection layer (114, fig 1) [page 5 line 17] on the first dielectric layer (116, fig 1) [page 5 line 17], and
wherein the antireflection layer (128, fig 1) includes:
a parallel layer portion (lateral portion of 128) that extends in a direction that is parallel to the first surface of the substrate (110b); and
a vertical layer portion (vertical portion of 128) and contacts the conductive reflection layer (136, fig 1).
Li does not teach the vertical portion extends from the parallel layer portion toward the second surface of the substrate.
wherein the vertical layer portion is at least partially surrounded by the conductive reflection layer, and the vertical layer portion comprises lateral surfaces and a bottom surface that are in contact with the conductive reflection layer.
Yoon teaches the vertical portion (vertical portion of 26 in the trench, fig 22) [0084] extends from the parallel layer portion (top portion of 26, fig 22) [0084] toward the second surface of the substrate (top to bottom of 41) [0084].
wherein the vertical layer portion (vertical portion of 26 in the trench, fig 22) [0084] is at least partially surrounded (left/right /bottom, fig 22) by the conductive reflection layer (23, fig 22), and the vertical layer portion (vertical portion of 26 in the trench, fig 22) [0084] comprises lateral surfaces (left to right 26 in the trench, fig 22) and a bottom surface (bottom of 26 , fig 22) that are in contact with the conductive reflection layer (23, fig 22).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yoon into the structure of Li to include the vertical portion extends from the parallel layer portion toward the second surface of the substrate.
wherein the vertical layer portion is at least partially surrounded by the conductive reflection layer, and the vertical layer portion comprises lateral surfaces and a bottom surface that are in contact with the conductive reflection layer as claimed.
The ordinary artisan would have been motivated to modify Li based on the teaching of Yoon in the above manner for the purpose of preventing the function of the conductive layer being deteriorated.
Further, it has been held that rearranging part of an invention involves only routine skill in the art, In re Japikse, 86 USPQ 70.
Claims 2 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li modified by Yoon as applied to claim 10 and further in view of Chiang et al (US20190096929A1).
Re claim 2 Li in view of Yoon teaches the image sensor of claim 10, wherein the first device isolation pattern (108, fig 1) is in an extension trench (322, fig 1) [page 4, line 39]
Li and Yoon do not teach the extension trench comprises curved portion, and the curved portion is between the first device isolation pattern and the second device isolation pattern.
Chiang teaches the extension trench (802, fig 8) [0033] comprises a curved portion (see fig 8), and the curved portion is between the first device isolation pattern (BDTI, fig 1) and the second device isolation pattern (110, fig 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chiang into the structure of Li and Yoon to include the extension trench comprises a curved portion, and the curved portion is between the first device isolation pattern and the second device isolation pattern as claimed.
The ordinary artisan would have been motivated to modify by Li and Yoon based on the teaching of Chiang in the above manner doing so the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved [0016].
Furthermore, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Re claim 18 Li in view of Yoon teach the image sensor of claim 10, wherein the first device isolation pattern (108, fig 1) is in an extension trench (322, fig 1) [page 4, line 39] and
wherein the second device isolation pattern (106, fig 1) [page 5, line is in a deep trench (Abstract) [page 1, lines 11-37] separated from the antireflection layer (128, fig 1) by the extension trench (306, fig 2) [page 4, line 35].
Li and Yoon do not teach the extension trench comprises a curved portion, and the curved portion is between the first device isolation pattern and the second device isolation pattern,
Chiang teaches the extension trench (802, fig 8) [0033] comprises a curved portion (see fig 8), and the curved portion is between the first device isolation pattern (BDTI, fig 1) and the second device isolation pattern (110, fig 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chiang into the structure of Li and Yoon to include the extension trench comprises a curved portion, and the curved portion is between the first device isolation pattern and the second device isolation pattern as claimed.
The ordinary artisan would have been motivated to modify by Li and Yoon based on the teaching of Chiang in the above manner doing so the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved [0016].
Furthermore, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Li modified by Yoon as applied to claim 10 and further in view of Kuo et al (US 20190165026A1).
Re claim 11 Li in view of Yoon teaches the image sensor of claim 10,
Li and Yoon do not teach a bottom surface of the vertical layer portion extends from the second surface of the substrate by a first distance, a bottom surface of the first dielectric layer extends from the second surface of the substrate by a second distance, and the first distance is greater than the second distance.
Kuo teaches a bottom surface of the vertical layer portion (bottom surface of vertical portion of 304, fig 3) [Kuo 0059] extends from the second surface of the substrate (top 102) [Kuo, 0019] by a first distance (vertical distance of 304), a bottom surface of the first dielectric layer (306, fig 3)[Kuo, 0036] extends from the second surface (top of 102) [Kuo, 0019] of the substrate by a second distance (vertical distance of 306 from top of the trench to the bottom of the trench, fig 3), and the first distance is greater than the second distance (vertical distance of 304 is greater than vertical distance of 306, see fig 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kuo into the structure of Li and Yoon to include a bottom surface of the vertical layer portion extends from the second surface of the substrate by a first distance, a bottom surface of the first dielectric layer extends from the second surface of the substrate by a second distance, and the first distance is greater than the second distance as claimed.
It would have been motivated to modify Li and Yoon based on the teaching of Kuo in the above manner for the purpose of improving quantum efficiency (QE) and modulation transfer function of the image sensor [0016].
Re claim 12 Li in view of Kuo teach the image sensor of claim 10, wherein a bottom surface of the parallel layer portion (lateral portion of 128, fig 1) [Li, page 5, line 47] contacts a top surface of the first dielectric layer (116, fig 1) [page 5, line 8] and a top surface of the conductive reflection layer (top of 114, fig 1) [Li, page 5, line 8].
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Li modified by Kuo in view of Velichko et al (US 20170229496 A1).
Re claim 13 Li in view of Yoon teaches the image sensor of claim 10, wherein the second device isolation pattern (106, fig 1) comprises:
a buried layer (110, fig 1);
a dielectric liner (112, fig 1) on the conductive liner.
Li and Yoon do not teach a conductive liner on the buried layer; and
the dielectric liner on the conductive liner.
Velichko does teach a conductive liner (124, fig 7) [0025] on the buried layer (136, fig 7) [0031]; and
the dielectric liner (122, fig 7) [0025] on the conductive liner (124, fig 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Velichko into the structure of Li and Kuo to include a conductive liner on the buried layer; and
the dielectric on the conductive liner a conductive liner on the buried layer; and the
dielectric on the conductive liner as claimed.
The ordinary artisan would have been motivated to modify Li and Yoon based on the teaching of Velichko in the above manner for the purpose of improving the performance of pixel [0028].
Re claim 16 Li in view Yoon and Velichko teach the image sensor of claim 13, wherein the conductive reflection layer (114, fig 1) [Li, page 5, line 22] comprises at least one of Cu, Al, W (Tungsten), Ti, and Ag. Li
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Li modified by Yoon in view of Velichko as applied to claims 10 and 13 and further in view of Park et al (US20130323875A1).
Re claim 14 Li in view of Yoon and Velichko teach the image sensor of claim 13,
Li, Yoon and Velichko do not teach a width of the conductive liner is greater than a width of the vertical layer portion.
Park does teach a width of the conductive liner (122a, fig 4J) [0173] is greater than a width of the vertical layer portion (116 in the left trench, fig 4J) [0128].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Li, Yoon and Velichko into the structure of Park to include a width of the conductive liner is greater than a width of the vertical layer portion as claimed.
The ordinary artisan would have been motivated to modify Li, Yoon and Velichko based on the teaching of Park in the above manner for the purpose of improve the light receiving efficiency and light sensitivity of pixels [0003].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Li modified Yoon and Velichko as applied to claims 10 and 13 further in view of Chen et al (US20230089511A1).
Re claim 15 Li in view of Yoon and Velichko teach the image sensor of claim 13, wherein:
the buried layer (110, fig 1) [Li page 5, line 13] comprises polysilicon (polysilicon) [page 5, line 13] or SiO₂.
Li, Yoon and Velichko do not teach the conductive liner comprises boron-doped silicon.
Chen teaches in fig 9 the conductive liner (214, fig 8) [0016] comprises boron-doped silicon [0016].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chen into the structure of Li, Yoon and Velichko to include the conductive liner comprises boron-doped silicon as claimed.
The ordinary artisan would have been motivated to modify Li, Yoon and Velichko based on the teaching of Chen in the above manner for the purpose to improving the optical performance [0019].
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use of a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Li modified by Yoon and Velichko as applied to claims 10 and 13 further in view of Jung et al (US20060027844A1)
Re claim 17 Li in view of Yoon and Velichko teach the image sensor of claim 13,
Li, Yoon and Velichko do not teach a top surface of the dielectric liner comprises a curved surface and a flat surface that is parallel to the first surface of the substrate.
Jung teaches a top surface of the dielectric liner comprises a curved surface and a flat surface that is parallel to the first surface of the substrate.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Jung into the structure of Li, Yoon and Velichko to include a top surface of the dielectric liner comprises a curved surface and a flat surface that is parallel to the first surface of the substrate as claimed.
The ordinary artisan would have been motivated to modify Li, Yoon and Velichko based on the teaching of Jung in the above manner for the purpose of improving operation characteristics and reliability of the image sensor [0064].
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (CN109638026B) in view of Velichko et al (US 20170229496 A1) and Yoon et al (US20150372031A1).
Re claim 19 Li teaches image sensor, comprising:
a substrate (100, fig 1) [page 5, line 6] that comprises a first surface (100b, fig 1) [Page 5 line 16] and a second surface (100ba, fig 1) [page 5 line 16] that are opposite to each other (see fig 1), wherein the substrate (100, fig 1) [page 5 line 6] comprises a plurality of pixel areas (plurality of 102, fig 1);
a plurality of microlenses (132, fig 1) [page 5, line 48] on the first surface (100b, fig 1) of the substrate (100);
a transfer gate (120, fig 1) [page 5 line 43] on the second surface (100a) of the substrate (1000, fig 1);
an isolation pattern (108/106, fig 1) [page 5, line 8] that extends from the first surface (100b, fig 1) and into the substrate (100, fig 1),
wherein the isolation pattern (108/106, fig 1) [page 5, line 8] is between the plurality of pixel areas (area of 102, fig 1) [page 5 line 6]; and
an antireflection layer (128, fig 1) [page 5 line 47] on the isolation pattern (108/106), wherein the isolation pattern (108/106, fig 1) comprises:
a first device isolation pattern (108, fig 1) that contacts the antireflection layer (128, fig 1); and
a second device isolation pattern (106, fig 1) that is spaced apart from the antireflection layer (128, fig 1),
wherein the first device isolation pattern (108) comprises:
a first dielectric layer (116, fig 1) [page 5 line 17]; and
a conductive reflection layer (114, fig 1) [page 5 line 17] on the first dielectric layer (116, fig 1) [page 5, line 17],
wherein the second device isolation pattern (106, fig 1) [page 5, line 8] comprises:
a buried layer (110, fig 1) [page 5 line 10];
and a dielectric liner (112, fig 1) [page 5 line 10], and
wherein the antireflection layer (128, fig 1) includes:
a parallel layer portion (bottom lateral portion of 128, fig 1) that is parallel to the first surface (100b, fig 1) of the substrate (100); and
a vertical layer portion (vertical portion of 128, fig 1)
Li does not teach second device pattern comprises a conductive liner on the buried layer and the dielectric liner on the conductive liner.
Velichko teaches second device pattern (pattern in 114, fig 7) [0023] comprises a conductive liner (124, fig 7) [0025] on the buried layer (136, fig 7) [0031] and the dielectric liner (122, fig 7) on the conductive liner (124, fig 7). [0025]
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Velichko into the structure of Li to include second device pattern comprises a conductive liner on the buried layer and the dielectric liner on the conductive liner as claimed.
The ordinary artisan would have been motivated to modify Li based on the teaching of Velichko in the above manner for the purpose of improving the performance of pixel [0028].
Li and Velichko do not teach the vertical portion that extend from the parallel layer portion and toward the second surface of the substrate, wherein the vertical layer portion contacts the conductive reflection layer.
wherein the vertical layer portion is at least partially surrounded by the conductive reflection layer, and the vertical layer portion comprises lateral surfaces and a bottom surface that are in contact with the conductive reflection layer.
Yoon teaches the vertical portion (vertical portion of 26 in the trench, fig 22) [0084] extends from the parallel layer portion (top portion of 26, fig 22) [0084] and toward the second surface of the substrate (top to bottom of 41) [0084], wherein the vertical layer portion contacts the conductive reflection layer (23, fig 22) [0084].
wherein the vertical layer portion (vertical portion of 26 in the trench, fig 22) [0084] is at least partially surrounded (left/right /bottom, fig 22) by the conductive reflection layer (23, fig 22), and the vertical layer portion (vertical portion of 26 in the trench, fig 22) [0084] comprises lateral surfaces (left to right 26 in the trench, fig 22) and a bottom surface (bottom of 26 , fig 22) [0084] that are in contact with the conductive reflection layer (23, fig 22).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yoon into the structure of Li and Velichko to include the vertical portion extends from the parallel layer portion toward the second surface of the substrate.
wherein the vertical layer portion is at least partially surrounded by the conductive reflection layer, and the vertical layer portion comprises lateral surfaces and a bottom surface that are in contact with the conductive reflection layer as claimed.
The ordinary artisan would have been motivated to modify Li and Velichko based on the teaching of Yoon in the above manner for the purpose of preventing the function of the conductive layer from deteriorating.
Further, it has been held that rearranging part of an invention involves only routine skill in the art, In re Japikse, 86 USPQ 70.
Re claim 20 Li in view of Velichko and Kuo teach the image sensor of claim 19, wherein:
a bottom surface of the first dielectric layer (bottom of 116, fig 1) [Li, page 5 line 17] contacts a top surface of the dielectric liner (112, fig 1) [Li page 5 line 10], and the first dielectric layer (bottom of 116, fig 1) [Li, page 5, line 17] and the dielectric liner (112, fig 1) [Li page 5, line 10] include different materials. (dielectric liner (112-Si₃N₄) and the first dielectric layer (116 Al₂O₃, fig 1) [Li page 5].
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ihara et al (US20160172391A1) teaches a method of fabricating Image Sensors having deep trenches including negative charge material. Okazaki (US20210217789A1) teaches a solid-state imaging device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/8/26
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