DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species C of Fig. 8C, claims 1-20, in the reply filed on July 2, 2026 is acknowledged. Therefore, claims 1-20 are presented for examination.
Claim Objections
Claim 13 is objected to because of the following informalities:
On line 11, a word “extends” should be amended with “extend”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6, 9-10 and 20 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Lee et al. (US 2023/0402097, Foreign priority: Jun. 10, 2022 (KR); hereinafter Lee).
Regarding claim 1, Lee discloses for a semiconductor memory device comprising that
a peripheral circuit structure (peripheral circuit structure PS, Fig. 6A) comprising peripheral circuits (transistors in PS, Fig. 6A);
a stacked structure (stack ST, Fig. 6A) on the peripheral circuit structure (PS, Fig. 6A) and comprising first electrode layers (gate electrodes GE, Fig. 6A) and first inter-electrode insulating layers (insulating layers ILD, Fig. 6A) that are alternately stacked (ST, Fig. 6A);
a first vertical pattern (vertical pattern VP/PAD1, Fig. 7A) that extends into the stacked structure (ST, Fig. 6A);
a first insulating layer (first upper insulating layer UIL1, Figs. 6A,7A) on the stacked structure (ST, Fig. 6A), a second electrode layer (first string selection line SSL1, Fig. 6A) on the first insulating layer (UIL1, Fig. 6A), because “each of the first and second string selection lines SSL1 and SSL2 is composed of a single conductive line” ([0070]), and a second insulating layer (second upper insulating layer UIL2, Figs. 6A,7A) on the second electrode layer (SSL1, Figs. 6A,7A);
a line separation pattern (separation structure SS1 or SS2, Fig. 6A) that extends into the second insulating layer (UIL2, Fig. 6A), the second electrode layer (SSL1, Fig. 6A), and the first insulating layer (UIL1, Fig. 6A); and
a second vertical pattern (upper channel pattern UVP of upper vertical structure UVS, Fig. 7A) that extends into the second insulating layer (UIL2, Fig. 7A), the second electrode layer (SSL1, Fig. 7A), and the first insulating layer (UIL1, Fig. 7A), wherein the second vertical pattern (UVP, Fig. 7A) is electrically connected to the first vertical pattern (VP/PAD1, Fig. 7A), because the upper channel pattern UVP of the upper vertical structure UVS by Lee is electrically connected to vertical pattern VP through the first conductive pad (PAD1, Fig. 7A).
Regarding claim 6, Lee further discloses for the semiconductor memory device of claim 1 that a source layer (source structure CST, Fig. 6A) that is on the second insulating layer (UIL2, Fig. 6A) and on the second vertical pattern (UVP of upper vertical structure UVS, Fig. 7A), because Applicant does not specifically claim what orientation a source layer has and/or a source layer is directly on the second insulating layer and on the second vertical pattern, the source structure by Lee is formed on the lower side of the second upper insulating layer UIL2 and the upper vertical structure UVS (Fig. 7A).
Regarding claim 9, Lee further discloses for the semiconductor memory device of claim 1 that an upper end of the first vertical pattern (upper surface of VP/PAD1, i.e., top surface of PAD1, Fig. 7A) extends from the peripheral circuit structure (PS, Fig. 6A) by a first distance;
an upper surface of the stacked structure (upper surface of ST, i.e., top surface of the uppermost ILD of ST, Fig. 7A) extends from the peripheral circuit structure (PS, Fig. 6A) by a second distance;
the first distance is greater than or equal to the second distance, because the top surface of the PAD1 and the uppermost ILD of ST is coplanar, therefore the distances from the peripheral structure PS are equal; and
the semiconductor memory device further comprises a first impurity region on the upper end of the first vertical pattern (PAD1, Fig. 6A), because “first conductive pads PAD1 may be formed in upper portions of the lower channel patterns VP. The first conductive pads PAD1 may be an impurity region, which is doped with impurities, or may be formed of a conductive material.” (emphasis added, [0085])
Regarding claim 10, Lee further discloses for the semiconductor memory device of claim 1 that a first gate insulating layer (data storage pattern DSP, Fig. 7A) between the first vertical pattern (VS/PAD1, Fig. 7A) and the first electrode layers (GE, Fig. 7A); and
a second gate insulating layer (gate insulating layer of UVS, Fig. 7A) between the second vertical pattern (UVP of UVS, Fig. 7A) and the second electrode layer (SSL1, Fig. 7A),
wherein the first gate insulating layer (DSP, Fig. 7A) comprises a tunnel insulating layer (tunnel insulating layer TIL, Fig. 7A), a charge storage layer (charge storing layer CIL, Fig. 7A) on the tunnel insulating layer (TIL, Fig. 7A), and a blocking insulating layer (blocking insulating layer BLK, Fig. 7A) on the charge storage layer (CIL, Fig. 7A),
wherein the first gate insulating layer (DSP, Fig. 7A) extends from a side of the first vertical pattern (side of VP, Fig. 7A) toward a side surface of the stacked structure (toward GE and ILD of ST, Fig. 7A), and wherein the second gate insulating layer (GIL of UVS, Fig. 7A) does not comprise the charge storage layer (no data storage pattern DSP, Fig. 7A).
Regarding claim 20, Lee discloses for an electronic system comprising that
a semiconductor memory device (Fig. 14) comprising a substrate (first substrate 1211, Fig. 14), a peripheral circuit structure (PERI, Fig. 14) on the substrate (1211, Fig. 14), and a cell array structure (CELL, Fig. 14) on the peripheral circuit structure (PERI, Fig. 14); and
a controller (circuit devices 1220a, Fig. 14) that is electrically connected to the semiconductor memory device (CELL region, Fig. 14) through an input/output pad (first input/output pad 1205 and second input/output pad 1305, Fig. 14) and is configured to control the semiconductor memory device (Fig. 14),
wherein the cell array structure (CS, Fig. 6A) comprises:
a stacked structure (ST, Fig. 6A) that is on the peripheral circuit structure (PS, Fig. 6A) and comprises first electrode layers (GE, Fig. 6A) and first inter-electrode insulating layers (ILD, Fig. 6A) that are alternately stacked (Fig. 6A);
a first vertical pattern (VS/PAD1, Fig. 7A) that extends into the stacked structure (ST, Fig. 7A);
a first insulating layer (UIL1, Fig. 7A) on the stacked structure (ST, Fig. 7A), a second electrode layer (SSL1 or SSL2, Fig. 7A) on the first insulating layer (UIL1, Fig. 7A), and a second insulating layer (UIL2, Fig. 7A) on the second electrode layer (SSL1 or SSL2, Fig. 7A);
a line separation pattern (SS1 and SS2, Fig. 6A) that extends into the second insulating layer (UIL2, Fig. 6A), the second electrode layer (SSL1 or SSL2, Fig. 6A), and the first insulating layer (UIL1, Fig. 6A); and
a second vertical pattern (UVP of UVS, Fig. 7A) that extends into the second insulating layer (UIL2, Fig. 7A), the second electrode layer (SSL1 or SSL2, Fig. 7A), and the first insulating layer (UIL1, Fig. 7A), wherein the second vertical pattern (UVP of UVS, Fig. 7A) is electrically connected to the first vertical pattern (VP/PAD1, Fig. 7A), because the upper channel pattern UVP of the upper vertical structure UVS by Lee is electrically connected to vertical pattern VP through the first conductive pad (PAD1, Fig. 7A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 13, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over by Lee et al. (US 2023/0402097, Foreign priority: Jun. 10, 2022 (KR); hereinafter Lee).
Regarding claim 2, Lee further discloses for the semiconductor memory device of claim 1 that a plurality of the line separation patterns (SS1/SS2, Fig. 6A)
Lee does not explicitly disclose that the plurality of line separation patterns (SS1/SS2, Fig. 6A) separate the second electrode layer (SSL1, Fig. 7A) into a plurality of ground selection lines.
However, because Applicant originally disclosed that “the third electrode layer GE3 may be a ground selection gate pattern GGE. The ground selection gate pattern GGE may also be called a ground select line” ([0069] of the present application), therefore, the term “ground selection lines” merely identifies the intended use of a conductive electrodes rather than requiring any particular structural distinction. Lee further discloses that the separation structure SS1 and SS2 divide the uppermost conductive electrodes SSL1 from the adjacent conductive electrode SSL2, and therefore, one of ordinary skill in the semiconductor memory art would have recognized that the separated conductive electrodes, including SSL2, are capable of serving as ground selection lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the separated conductive electrodes of Lee as the claimed ground selection lines, because doing so merely constitutes the use of a known conductive electrode for its recognized function in a 3D semiconductor memory device.
Regarding claim 3, Lee further discloses that the plurality of line separation patterns (SS1/SS2, Fig. 6A) comprise first line separation patterns (SS1, Fig. 6A) and second line separation patterns (SS2, Fig. 6A),
wherein the semiconductor memory device further comprises:
block separation patterns (lower portion of SS1 and SS2, Fig. 6A) that extend into the stacked structure (ST, Fig. 6A) and separate the stacked structure (ST, Fig. 6A) into a plurality of blocks (Fig. 6A), because Applicant does not specifically claim what material’s composition block separation patterns has and/or what structural relationship between block separation patterns and line separation patterns has, Applicant originally disclosed that “the block separation patterns SS1, the first center separation pattern SS2, and the second center separation pattern SS3 may each have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride” ([0095]) and “the string line separation pattern 9 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride” ([0099]), therefore, in view of the present application, the line separation pattern GCT1 and the block separation pattern SS1 can be made of the same material as a single body; in this case, the upper portion of SS1 and SS2 can correspond to the first and second line separation patterns in the claimed invention and the lower portion of SS1 and SS2 can correspond to the block separation patterns in the claimed invention, respectively; and
wherein the first line separation patterns (upper portion of SS1, Fig. 6A) are respectively on the block separation patterns (lower portion of SS1, Fig. 6A), and wherein the second line separation patterns (upper portion of SS2, Fig. 6A) are respectively on the center separation patterns (lower portion of SS2, Fig. 6A).
Lee does not explicitly disclose that center separation patterns that extend into the stacked structure and are respectively at a center of each of the plurality of blocks.
However, it would have been obvious to one of ordinary skill in the art to arrange the separation patterns in an array corresponding to the plurality of memory blocks, since semiconductor memory devices commonly include a plurality of memory arrays. Under such an arrangement, a respective separation structure SS1 or SS2 in Lee would be located at the center of each corresponding block, thereby satisfying the claimed “center separation patterns” extending into the stacked structure and respectively positioned at the center of each of the plurality of blocks.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide separation structures between adjacent memory blocks in Lee’s semiconductor memory device, as disclosed by Lee.
Regarding claim 13, Lee further discloses for a semiconductor memory device comprising that
a substrate (first substrate 1201, Fig. 14);
a peripheral circuit structure (PERI, Fig. 14) comprising peripheral circuits (circuit devices 1220b in PERI, Fig. 14) that are on the substrate (1201, Fig. 14), the peripheral circuit structure (PERI, Fig. 14) comprising first bonding pads (lower bonding metals 1271b/1272b, Fig. 14) that are electrically connected to the peripheral circuits (1220b, Fig. 14); and
a cell array structure (CELL, Fig. 14) comprising second bonding pads (upper bonding metals 1371b/1372b, Fig. 14) that are electrically connected to the first bonding pads (1271b/1272b, Fig. 14),
wherein the cell array structure (CS, Fig. 6A) comprises:
a stacked structure (ST, Fig. 6A) comprising first electrode layers (GE, Fig. 6A) and first inter-electrode insulating layers (ILD, Fig. 6A) that are alternately stacked (Fig. 6A);
block separation patterns (lower portion of SS1, Fig. 6A) that extends into the stacked structure (ST, Fig. 6A);
a center separation pattern (lower portion of SS2, Fig. 6A) that extends into the stacked structure (ST, Fig. 6A) and is between the block separation patterns (lower portion of SS1, Fig. 6A), because semiconductor memory devices commonly include a plurality of memory arrays, and therefore, under such an arrangement, a respective separation structure SS1 or SS2 would be located at the center of each corresponding block, thereby satisfying the claimed “a center separation pattern” positioned at the center of each of the plurality of blocks;
first vertical patterns (VP/PAD1, Fig. 7A) that extend into the stacked structure (ST, Fig. 7A);
a first insulating layer (UIL1, Fig. 7A) on the stacked structure (ST, Fig. 7A), a second electrode layer (SSL1 or SSL2, Fig. 7A) on the first insulating layer (UIL1, Fig. 7A), and a second insulating layer (UIL2, Fig. 7A) on the second electrode layer (SSL1 or SSL2, Fig. 7A);
a first line separation pattern (upper portion of SS1, Fig. 6A) that extends into the second insulating layer (UIL2, Fig. 6A), the second electrode layer (SSL1 or SSL2, Fig. 6A), and the first insulating layer (UIL1, Fig. 6A),
wherein the first line separation patterns (upper portion of SS1, Fig. 6A) are respectively on the block separation patterns (lower portion of SS1, Fig. 6A);
a second line separation pattern (upper portion of SS2, Fig. 6A) that extends into the second insulating layer (UIL2, Fig. 6A), the second electrode layer (SSL1 or SSL2, Fig. 6A), and the first insulating layer (UIL1, Fig. 6A),
wherein the second line separation pattern (upper portion of SS2, Fig. 6A) is on the center separation pattern (lower portion of SS2, Fig. 6A), because Applicant does not specifically claim what material’s composition block separation patterns and a center separation pattern has and/or what structural relationship between block separation patterns/a center separation pattern and line separation patterns has, Applicant originally disclosed that “the block separation patterns SS1, the first center separation pattern SS2, and the second center separation pattern SS3 may each have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride” ([0095]) and “the string line separation pattern 9 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride” ([0099]), therefore, in view of the present application, the line separation pattern GCT1, the block separation pattern SS1, center separation patterns SS2/SS3 can be made of the same material as a single body; in this case, the upper portion of SS1 and SS2 can correspond to the first and second line separation in the claimed invention and the lower portion of SS1 and SS2 can correspond to the block separation pattern and center separation pattern in the claimed invention, respectively; and
second vertical patterns (UVP of UVS, Fig. 7A) that extend into the second insulating layer (UIL2, Fig. 7A), the second electrode layer (SSL1 or SSL2, Fig. 7A), and the first insulating layer (UIL1, Fig. 7A), wherein the second vertical patterns (UVP of UVS, Fig. 7A) are respectively on the first vertical patterns (VP/PAD1, Fig. 7A, also see Fig. 6A).
Regarding claim 16, Lee further discloses that a source layer (source structure CST, Fig. 6A) that is on the second insulating layer (UIL2, Fig. 6A) and is on the first line separation pattern (upper portion of SS1, Fig. 6A), the second line separation pattern (upper portion of SS2, Fig. 6A), and the second vertical patterns (UVP of UVS, Fig. 6A), because Applicant does not specifically claim what orientation a source layer has and/or a source layer is directly on the second insulating layer and on the first line separation pattern, the second line separation pattern, and the second vertical patterns, the source structure by Lee is formed on the lower side of the second upper insulating layer UIL2 and the upper vertical structure UVS (Fig. 6A).
Regarding claim 19, Lee further discloses that an upper end of a given first vertical pattern from among the first vertical patterns (upper surface of VP/PAD1, i.e., top surface of PAD1, Fig. 7A) extends from the substrate by a first distance;
an upper surface of the stacked structure (upper surface of ST, i.e., top surface of the uppermost ILD of ST, Fig. 7A) extends from the substrate by a second distance;
the first distance is greater than or equal to the second distance, because the top surface of the PAD1 and the uppermost ILD of ST is coplanar, therefore the distances from the substrate are equal, and
the semiconductor memory device further comprises a first impurity region on the upper end of the given first vertical pattern (PAD1, Fig. 7A), because “first conductive pads PAD1 may be formed in upper portions of the lower channel patterns VP. The first conductive pads PAD1 may be an impurity region, which is doped with impurities, or may be formed of a conductive material.” (emphasis added, [0085]).
Allowable Subject Matter
Claims 4-5, 7-8, 11-12, 14-15 and 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art cited in this Office Action does not teach the claimed limitations, “… the center separation patterns comprises a discontinuous section in the connection region” of claims 4 and 14, “… are coplanar with…” of claims 5 and 15, “at least one of third electrode layer” of claims 7 and 17, “the at least one third electrode layer” of claims 8 and 18, and “the second electrode layer is directly on the second gate insulating layer” of claim 11, “… has a nonlinear shaped cross section” of claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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