DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 18-20 and 22-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (U.S. Publication No. 2021/0296424).
Regarding claim 1, Cho teaches a display device comprising:
a data driving circuit (Fig. 3, circuit 40) configured to supply a plurality of data voltages to a plurality of data lines (data lines D1, D2, etc.), wherein the plurality of data lines comprise a plurality of first data lines and a plurality of second data lines (not labeled, but first lines in area 13, second lines in areas 11 and 12);
a gate driving circuit (Fig. 6, slk1-3) configured to supply a plurality of gate signals to a plurality of gate lines (not specifically shown, but inherent that gate lines are present in display for it to function); and
a display panel (Fig. 3) having the plurality of first data lines (D8-D14, etc.) disposed in a first area corresponding to the data driving circuit (area 10, 13), and the plurality of second data lines (D1-7, Dm, Dm-1, etc.) disposed in a second area located outside of the first area (second areas 11 and 12),
wherein the display panel includes:
a plurality of first data link lines (60b) for connecting the plurality of the first data lines to the data driving circuit (Fig. 3); and
a plurality of second data link lines (60a and DM1-DM7) with connecting paths (DM1-7) arranged in a stepped line configuration (see Fig. 3, stepped configuration for DM1-7), for connecting the plurality of second data lines to the data driving circuit (Fig. 3).
Regarding claim 18, Cho teaches the display device according to claim 1, wherein some of the plurality of second data link lines are disposed in a display area of the display panel, which is different from a bezel area of the display panel (see Fig. 3).
Regarding claim 19, Cho teaches a display panel comprising:
a plurality of subpixels (see Fig. 3, PX) configured to display an image;
a plurality of first data lines (D8-D14, etc.) disposed in a first area corresponding to a data driving circuit (driving circuit 40);
a plurality of second data lines (D1-7) disposed in a second area located outside of the first area (Fig. 3);
a plurality of first data link lines (60b) for connecting the plurality of first data lines to the data driving circuit (Fig. 3); and
a plurality of second data link lines (60a) having connecting paths arranged in a stepped line configuration (Fig. 3), for connecting the plurality of second data lines to the data driving circuit (Fig. 3).
Regarding claim 20, Cho teaches the display panel according to claim 19, wherein the plurality of second data link lines and the plurality of subpixels are disposed in a display area of the display panel (Fig. 3).
Regarding claim 22, Cho teaches the display panel according to claim 19, wherein the plurality of second data link lines are disposed perpendicular to each other (Fig. 3).
Regarding claim 23, Cho teaches a display device comprising:
the display panel according to claim 19; and
the data driving circuit disposed at one side of the display panel (Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Tian (U.S. Publication No. 2024/0237444)
Regarding claim 2, Cho teaches the display device according to claim 1, wherein the plurality of first data lines are connected to the data driving circuit through the plurality of first data link lines in a straight line configuration.
However, Tian teaches a similar display in which the data link lines connecting the driving circuit to the first data lines are straight (see Tian Fig. 17, first link lines 1602 are straight and connect directly to data lines 1607, paragraph [0186]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the lines of Cho could have been straight instead of fanned out because this allows for identical lengths for all data link lines, and therefore identical resistance and a more even display.
Regarding claim 21, Cho teaches the display panel according to claim 19, wherein all the plurality of first data link lines are disposed in a bezel area of the display panel (Fig. 3), but does not teach all the plurality of first link lines extend in a straight line through the entire bezel area. However, Tian teaches a similar display in which the data link lines connecting the driving circuit to the first data lines are straight (see Tian Fig. 17, first link lines 1602 are straight and connect directly to data lines 1607, paragraph [0186]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the lines of Cho could have been straight instead of fanned out because this allows for identical lengths for all data link lines, and therefore identical resistance and a more even display.
Allowable Subject Matter
Claims 3-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3-17, the prior art, alone or in combination, fails to teach or suggest a plurality of (2-3)th data link lines, for connecting the plurality of (2-2)th data link lines to the second data lines through the connecting paths arranged in the stepped line configuration.
Conclusion
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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