DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 4, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 8,486,802 B2; hereinafter Jang) in view of Lee et al. (US 2012/0187403 A1; hereinafter Lee).
Regarding Claim 1, Jang suggests an apparatus (Fig. 4, device), comprising:
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a plurality of active regions (Fig. 4, items 110) on a semiconductor substrate (Fig. 4, item 100); an active bridge region (Fig. 4, item 170) connecting two active regions (Fig. 4, items 110) among the plurality of active regions (Fig. 4, items 110).
But Jang does not specific teach and a plurality of test circuit elements on the active bridge region and the two active regions.
However, Lee suggests and a plurality of test circuit elements (Fig. 3B, items 262) on the active bridge region (para [0067]; a bridge between the first test shared contacts 262) and the two active regions (Fig. 3B, items 220).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Jang in view of Lee because to detect the occurrence of a bridge between adjacent shared contacts, nodes are connected to the respective adjacent shared contacts, and then, it is determined whether current flows between the nodes or not (Lee, para[0008]).
Regarding Claim 2, Jang and Lee suggest the apparatus according to claim 1, Jang also discloses wherein the active bridge region (Fig. 4, item 170) and the two active regions (Fig. 4, items 110) have an elongated shape at least in one direction in a plan view (Fig. 4, it is a cross-sectional view).
Regarding Claim 3, Jang and Lee suggest the apparatus according to claim 2, Jang also discloses wherein the two active regions (Fig. 4, items 110) are arranged in line along the one direction with a gap (Fig. 4, trench isolation 120) therebetween, and the active bridge region (Fig. 4, item 170) fills the gap (Fig. 4, trench isolation 120).
Regarding Claim 4, Jang and Lee suggest the apparatus according to claim 2, Jang also discloses wherein the enlarged shape is spaced from other active regions (Fig. 4, items 110) among the plurality of active regions (Fig. 4, items 110) by at least one opening (column 6, lines 28 – 32; spacers 160 may be disposed along sidewalls 150a of the opening in the first ILD layer 150).
Regarding Claim 7, Jang and Lee suggest the apparatus according to claim 1, Lee also suggests wherein the test circuit elements include two bit contacts (para[0050]; first and second bit lines BL and /BL).
Regarding Claim 9, Jang and Lee suggest the apparatus according to claim 1, Lee also suggests wherein the test circuit elements include test transistor elements (para[0055]; the transistors formed at the regions overlapping the first conductivity type active regions).
Claim(s) 5, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Lee, and further in view of Wang et al. (US 9,606,155 B2; hereinafter Wang).
Regarding Claim 5, Jang and Lee suggest the apparatus according to claim 1. But Jang and Lee do not specifically teach wherein the test circuit elements include two capacitance contacts.
However, Wang suggests wherein the test circuit elements include two capacitance contacts (column 3, lines 63 – 67; reference capacitances in the stacked circuit layer with the under-test capacitances).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the combination of Jang and Lee in view of Wang because a result, the range of the under-test capacitances are measured accurately (Wang, column 3, lines 66 – 67).
Regarding Claim 6, Jang, Lee, and Wang disclose the apparatus according to claim 5, Lee also suggests wherein the test circuit elements further include at least one bit contact (para [0050]; first and second bit lines BL and /BL).
Regarding Claim 8, Jang and Lee suggest the apparatus according to claim 7. But Jang and Lee do not specifically teach wherein the test circuit elements further include at least one capacitance contact.
However, Wang suggests wherein the test circuit elements further include at least one capacitance contact (column 3, lines 63 – 67; reference capacitances in the stacked circuit layer with the under-test capacitances).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the combination of Jang and Lee in view of Wang because a result, the range of the under-test capacitances are measured accurately (Wang, column 3, lines 66 – 67).
Claim(s) 10 – 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Lee, in view of Wang, and further in view of Chen (US 2020/0243416 A1; hereinafter Chen).
Regarding Claim 10, Jang suggests an apparatus (Fig. 4, device), comprising:
a plurality of active regions (Fig. 4, items 110) on a semiconductor substrate (Fig. 4, item 100);
an active bridge region (Fig. 4, item 170) connecting two active regions (Fig. 4, items 110) arranged adjacently among the plurality of active regions (Fig. 4, items 110), the active bridge region (Fig. 4, item 170) and the two active regions (Fig. 4, items 110) forming an enlarged active region at least in one direction in a plan view (Fig. 4, it is a cross-sectional view).
But Jang does not specific teach and a plurality of test circuit elements on the enlarged active region or two bit contacts electrically connected to each other by the enlarged active region.
However, Lee suggests and a plurality of test circuit elements (Fig. 3B, items 262) on the enlarged active region (Fig. 4, items 220 and para [0067]; a bridge between the first test shared contacts 262) or two bit contacts electrically connected to each other by the enlarged active region (para[0050]; first and second bit lines BL and /BL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Jang in view of Lee because to detect the occurrence of a bridge between adjacent shared contacts, nodes are connected to the respective adjacent shared contacts, and then, it is determined whether current flows between the nodes or not (Lee, para [0008]).
But Jang and Lee do not specifically teach the plurality of test circuit elements including two capacitance contacts.
However, Wang suggests the plurality of test circuit elements including two capacitance contacts (column 3, lines 63 – 67; reference capacitances in the stacked circuit layer with the under-test capacitances).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the combination of Jang and Lee in view of Wang because a result, the range of the under-test capacitances are measured accurately (Wang, column 3, lines 66 – 67).
But Jang, Lee, and Wang do not specifically teach arranged in matrix in a scribe region.
However Chen suggests arranged in matrix in a scribe region (para [0054]; a wafer including the semiconductor device of the present disclosure may be scribe along the scribe lines).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the combination of Jang, Lee, and Wang in view of Chen in order to separate the dies from one another by mechanical or laser cutting methods (Chen, para [0054]).
Regarding Claim 11, Jang, Lee, Wang, and Chen suggest the apparatus according to claim 10, Jang also discloses wherein the at least two active regions (Fig. 4, items 110) are arranged in line along the one direction with a gap (Fig. 4, trench isolation 120) therebetween, and the active bridge region (Fig. 4, item 170) fills the gap (Fig. 4, trench isolation 120).
Regarding Claim 12, Jang, Lee, Wang, and Chen suggest the apparatus according to claim 10, Wang also suggests wherein the two capacitance contacts are coupled to a capacitance (column 3, lines 63 – 67; reference capacitances in the stacked circuit layer with the under-test capacitances).
Regarding Claim 13, Jang, Lee, Wang, and Chen suggest the apparatus according to claim 10, Lee also suggests wherein the two bit contacts (para [0050]; first and second bit lines BL and /BL) are coupled to a bit line (para[0050]; first and second bit lines BL and /BL).
Regarding Claim 14, Jang, Lee, Wang, and Chen suggest the apparatus according to claim 10, Lee also suggests wherein the two capacitance contacts or the two bit contacts are part of a test transistor (para[0055]; the transistors formed at the regions overlapping the first conductivity type active regions).
Regarding Claim 15, Jang, Lee, Wang, and Chen suggest the apparatus according to claim 10, Jang also discloses further comprising a plurality of word lines configured to be turned on and off during testing of a circuit electric property (column 5, lines 37 – 41; the semiconductor device may be a memory device, e.g., a flash memory device such as a NAND flash memory, that includes word lines and pairs of string select lines (SSL's), as well as various transistor structures, the transistor comprises a capability of turn on and off).
Claim(s) 16 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Lee, and further in view of Chen.
Regarding Claim 16, Jang suggests a test element group on a semiconductor substrate (Fig. 4, item 100), comprising: apparatus (Fig. 4, device), comprising:
a plurality of active regions (Fig. 4, items 110) in the scribe region;
an active bridge region (Fig. 4, item 170) connecting two active regions (Fig. 4, items 110) among the plurality of active regions (Fig. 4, items 110).
But Jang does not specific teach and a plurality of test circuit elements on the active bridge region and the two active regions.
However, Lee suggests and a plurality of test circuit elements (Fig. 3B, items 262) on the active bridge region (para [0067]; a bridge between the first test shared contacts 262) and the two active regions (Fig. 3B, items 220).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Jang in view of Lee because to detect the occurrence of a bridge between adjacent shared contacts, nodes are connected to the respective adjacent shared contacts, and then, it is determined whether current flows between the nodes or not (Lee, para [0008]).
But Jang and Lee do not specifically teach in a scribe region.
However Chen suggests in a scribe region (para [0054]; a wafer including the semiconductor device of the present disclosure may be scribe along the scribe lines).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the combination of Jang and Lee in view of Chen in order to separate the dies from one another by mechanical or laser cutting methods (Chen, para [0054]).
Regarding Claim 17, Jang, Lee, and Chen suggest the test element group according to claim 16, Jang also discloses wherein the bridge active region (Fig. 4, item 170) and the two active regions (Fig. 4, items 110) have an elongated shape at least in one direction in a plan view (Fig. 4, it is a cross-sectional view).
Regarding Claim 18, Jang, Lee, and Chen suggest the test element group according to claim 17, Jang also discloses wherein the two active regions (Fig. 4, items 110) are arranged in line along the one direction with a gap (Fig. 4, trench isolation 120) therebetween, and the active bridge region (Fig. 4, item 170) fills the gap (Fig. 4, trench isolation 120).
Regarding Claim 19, Jang, Lee, and Chen suggest the test element group according to claim 16, Lee also suggests wherein the test circuit elements are at least part of a test transistor (para[0055]; the transistors formed at the regions overlapping the first conductivity type active regions).
Regarding Claim 20, Jang, Lee, and Chen suggest the test element group according to claim 16, Jang also discloses wherein the test element group is at least part of a memory device (column 5, lines 37 – 41; the semiconductor device may be a memory device, e.g., a flash memory device such as a NAND flash memory, that includes word lines and pairs of string select lines (SSL's), as well as various transistor structures, the transistor comprises a capability of turn on and off).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. (US 8,865,482 B2) teaches a substrate under the semiconductor wafer, the substrate connects to a low potential; wherein there are several detection circuit structures disposed on the semiconductor wafer; the way of disposing one of the detection circuit structures includes the following steps: Step a, N-type active regions and P-type active regions are formed on the wafer; Step b, a silicon dioxide layer is applied on the wafer to separate the N-type active regions from the P-type active regions; the N-type active regions are formed in a P well and the P-type active regions are formed in an N well (see claim 1).
Kim (US 2009/0190387 A1) suggests a semiconductor device comprising: an active region formed in a substrate; a dummy active region formed in the substrate and separated from the active region; a word line crossing over the active region; and a dummy word line, formed over the dummy active region to overlap at least part of the dummy active region, having an end positioned within the dummy active region (see claim 1).
Choi (US 2007/0241420 A1) discloses a semiconductor device comprising: a device isolation structure formed in a semiconductor substrate to define an active region; a bridge type channel structure formed in the active region, wherein the bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction (see claim 1).
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/GIOVANNI ASTACIO-OQUENDO/ Primary Examiner, Art Unit 2858 12/27/2025