Prosecution Insights
Last updated: October 02, 2026
Application No. 18/441,962

ACTIVE MATERIALS FOR REDUCING HOT ELECTRON-INDUCED PUNCH-THROUGH AND RELATED APPARATUSES AND COMPUTING SYSTEMS

Final Rejection §102§103§112
Filed
Feb 14, 2024
Priority
Mar 13, 2023 — provisional 63/489,915
Examiner
CHOI, WOO H
Art Unit
3992
Tech Center
3900
Assignee
Micron Technology Inc.
OA Round
3 (Final)
84%
Grant Probability
Favorable
4-5
OA Rounds
4m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
76 granted / 91 resolved
+23.5% vs TC avg
Minimal -4% lift
Without
With
+-4.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
24 currently pending
Career history
113
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
20.9%
-19.1% vs TC avg
§102
14.0%
-26.0% vs TC avg
§112
29.7%
-10.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 91 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION 1. This Office Action is responsive to the amendments filed on March 9, 2026 and RCE filed on March 10, 2026 in response (“the Response”) to the Office Action issued on January 16, 2026. In the Response, applicant amended claims 1, 16, and 19. Claims 1-20 are pending. Response to Amendments and Arguments Claim Rejections - 35 USC § 112 3. Applicant asserts that paragraphs [0024] and [0046]-[0051] describe intentionally spacing adjacent active materials at the minimum allowable distance and that the specification thus makes clear that the spacing is not arbitrary, but is deliberately selected to correspond to the smallest spacing permitted by fabrication constraints. Applicant’s arguments are not persuasive because the paragraphs cited do not support the arguments. Paragraph [0024] defines the term “substantially” not “minimum tolerance distance” as Applicant appear to be arguing. Paragraphs [0046]-[0051] do not disclose that in the designs shown in FIGs 5-7, “a minimum tolerance distance” is the smallest spacing permitted by some undisclosed fabrication design rule. 4. Applicant also argues that the examiner “suggests that Applicant’s failure to quantify or compare distances shown in prior art constitutes evidence of indefiniteness.” The examiner notes that the rejection was not made in the first Office Action issued on July 29, 2025. The rejection was made in the last Office Action issued on January 16, 2026, only after Applicant argued that the prior art reference does not teach this “minimum tolerance distance” without any reasoned argument as to why the prior art reference does not teach this minimum tolerance distance and why this “distance” is patentably distinct from the distance between active regions taught in the prior art. It appears that Applicant’s arguments were based on nothing more than the fact that the inventors of the prior art patent application did not use the term “minimum tolerance distance” in the description of their invention. If Applicant considers this “minimum tolerance distance” to be the patentable subject matter, Applicant should present persuasive arguments explaining how the specification discloses this patentable distinction, not merely cite paragraphs as support for arguments. Applicant should also present persuasive argument as to why it would not be obvious to one skilled in the art to design a semiconductor device with minimum tolerable distance between active regions. The examiner also notes that while the rejection under 35 USC 112 in the last Office Action was based on Applicant’s seemingly arbitrary distinction between distances between active regions of prior art teachings and claims, the rejection in this Office Action is based on an undisclosed fabrication design rule. Claim Rejections - 35 USC § 102 5. Applicant argues that Yokomichi does not appear to disclose “a minimum tolerance distance permitted by a fabrication design rule.” This is not a persuasive argument because the specification does not disclose any fabrication design rule that specifies a permitted minimum tolerance. To be persuasive, Applicant must show what the fabrication rules were at the time of the invention, how Applicant’s design conforms to the rules, and how Yokomichi’s design fails to meet the minimum tolerance according to the rules. Merely amending the claims to recite an undisclosed fabrication design rule and asserting that the claimed design conforms to these undisclosed rules while the prior art design does not, amounts to a mere assertion not based on any evidence or actual disclosure. Applicant has not shown why Yokomichi’s design does not meet the minimum tolerance requirements under their own fabrication design rule. One skilled in the would have no reason to file for a patent for a design that does not meet their fabrication design rule. The examiner also notes that Yokomichi discloses adjusting the distance between adjacent active regions overlapped by the same gate electrodes to prevent leakage due to the hot electron induced punch-through (HEIP) in paragraphs [0049]-[0050]. One skilled in the art would understand this distance to prevents HEIP to be the minimum tolerance distance. Claim Rejections - 35 USC § 112 6. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 7. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims recite the limitation “a minimum tolerance distance permitted by a fabrication design rule.” The specification does not disclose any fabrication design rule, much less one that specifies a minimum tolerance distance. 8. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 9. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims recite the limitation “a minimum tolerance distance permitted by a fabrication design rule.” However, the specification does not disclose any fabrication design rule to determine this minimum, tolerance distance to be able to establish the metes and bounds of the claims. Claim Rejections - 35 USC § 102 10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 11. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 12. Claims 1-7, 9, 11, and 13-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2022/00254788 (“Yokomichi”). 13. With respect to claim 1, Yokomichi discloses an apparatus, comprising: a first active material (FIG.4, material of bottom region/structure of 406A) including a first outside edge (left edge) and a first inside edge opposite the first outside edge (right edge), the first outside edge defining a first notch reducing a width of the first active material relative to that of other portions of the first active material; a second active material (FIG. 4, 401A) spaced at substantially a minimum tolerance distance (distance between the right edge of the bottom structure of 406A and the left edge of 401A) permitted by a fabrication design rule (see paragraph [0049]. Yokomochi discloses adjusting the distance between adjacent active regions to prevent leakage due to hot electron induced punch-through (HEIP), i.e., minimum distance to prevent leakage due to HEIP) from the first inside edge of the first active material; a third active material (401B) spaced at substantially the minimum tolerance distance permitted by a fabrication design rule from the second active material (distance between 401A and 401B), the second active material between the first active material and the third active material (see FIG. 4); and a fourth active material (FIG. 4, shaded diffusion region of the middle structure of 406D) including a second outside edge and a second inside edge opposite the second outside edge, the second inside edge spaced at substantially the minimum tolerance distance (distance between the left edge of the middle structure of 406D next to 401B and the right edge of 401B) permitted by a fabrication design rule from the third active material, the third active material between the second active material and the fourth active material, the second outside edge defining a second notch reducing a width of the fourth active material relative to that of other portions of the fourth active material (see FIG. 4). 14. With respect to claim 2, Yokomichi discloses the apparatus of claim 1, further comprising a gate material overlapping with the first active material, the second active material, the third active material, and the fourth active material (see paragraph [0031]). 15. With respect to claim 3, Yokomichi discloses the apparatus of claim 2, wherein the gate material overlaps a portion of the first outside edge that defines the first notch and a portion of the second outside edge that defines the second notch (see FIG. 4). 16. With respect to claim 4, Yokomichi discloses the apparatus of claim 1, wherein the second outside edge faces an active material of an opposite type to that of the fourth active material (see FIG. 4, outer edge of P+ diffusion area of 406 faces N+ diffusion area of 409A). 17. With respect to claim 5, Yokomichi discloses the apparatus of claim 4, wherein the active material comprises an N-type active material (see FIG. 4, the apparatus comprises both P and N type active material) and the fourth active material includes a P-type active material (shaded area of 406D is of P-type). 18. With respect to claim 6, Yokomichi discloses the apparatus of claim 4, wherein a lateral area defined by the second outside edge and an edge of the active material is free of a floating active material (see FIG. 4, there is no floating active region). 19. With respect to claim 7, Yokomichi discloses the apparatus of claim 4, wherein a lateral area defined by the second outside edge and an edge of the active material is free of a polysilicon hammerhead material (see FIG. 4, there is no polysilicon hammerhead material). 20. With respect to claim 9, Yokomichi discloses the apparatus of claim 1, wherein the first inside edge and the second inside edge define notches (see FIG. 4). 21. With respect to claim 11, Yokomichi discloses the apparatus of claim 1, wherein edges of the second active material and the third active material define notches (see FIG. 4). 22. With respect to claim 13, Yokomichi discloses the apparatus of claim 1, wherein the first outside edge faces a memory cell array (see FIG. 4; see also paragraph [0041]). 23. With respect to claim 14, Yokomichi discloses the apparatus of claim 1, further comprising a subwordline driver (SWD) of a memory device, the SWD including a first transistor including at least a portion of the first active material, a second transistor including at least a portion of the second active material, a third transistor including at least a portion of the third active material, and a fourth transistor including at least a portion of the fourth active material (see FIG. 4 and paragraph [0033]-[0040]). 24. With respect to claim 15, Yokomichi discloses the apparatus of claim 1, further comprising shallow trench isolation (STI) materials between the first active material and the second active material, between the second active material and the third active material, and between the third active material and the fourth active material (see paragraph [0003]). 25. With respect to claim 16, see the rejection of claim 1 above. 26. With respect to claim 17, Yokomichi discloses the apparatus of claim 16, further comprising a subwordline driver (SWD) (paragraph [0031]) including the first transistor, the second transistor, the third transistor, and the fourth transistor, the SWD driven by a common main word line (MWL) signal (paragraph [0032]). 27. With respect to claim 18, Yokomichi discloses the apparatus of claim 16, wherein gate materials of the first transistor and the fourth transistor overlap with the first notch and the second notch (see FIG. 4). 28. With respect to claim 19, see the rejection of claim 1 above. Claim Rejections - 35 USC § 103 29. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 30. Claims 19 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yokomichi. 31. With respect to claim 8, Yokomichi discloses the apparatus of claim 1 s discussed above. However, Yokomichi does not specifically disclose that the first inside edge and the second inside edge are free of notches. However, Yokomichi discloses other active materials where the left edge is notched and right edge is free of notches (FIG 4., 409D) and vice versa (409C) providing evidence that the claimed edge configurations of the first and the fourth active material as known in the art. It would have been obvious to one of ordinary skill in the art to use a known shape of active region to control the distance between adjacent active regions overlapped by the same gate electrode to control leakage current due to the hot electron induced punch-through (HEIP) (see paragraph 49). Applying a known technique (i.e., known shape of edges) to a known device (i.e., memory device) ready for improvement to yield predictable result (i.e., control of distance between adjacent active regions) is obvious under KSR v Teleflex. 32. With respect to claim 19, Yokomichi discloses a memory device including a subwordline driver (SWD) as claimed in claim 19 (see the rejection of claim 1 above). To the extent that Yokomichi does not specifically disclose a computing system recited in the preamble, the examiner takes Official Notice that computing systems not only comprise a memory device, but memory is required in a functional computing system. 33. With respect to claim 20, Yokomichi discloses all of the limitations of the parent claim 19 as discussed above. Although Yokomich does not specifically disclose a computing system with the limitations claimed in claim 19, the examiner takes Official Notice that a computing systems comprising: one or more processors electrically connected to the memory device; one or more input devices electrically connected to the one or more processors; one or more non-volatile data storage devices electrically connected to the one or more processors; and one or more output devices electrically connected to the one or more processors is notoriously well known in the art. 34. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yokomichi in view of US 2023/0005519 (“Miyatake”). 35. With respect to claim 10, Yokomichi discloses all of the limitations of the parent claim. However, Yokomichi does not specifically disclose that the edges of the second active material and the third active material are free of notches. On the other hand, Miyatake discloses an apparatus with four adjacent active regions or material where the edges of the second active material and the third active material are free of notches (see FIG. 11B). It would have been obvious to one of ordinary skill in the art to combine the teachings of Yokomich and Miyatake to configure the edges to be able to control the distance between active regions as discussed above. One skilled in the art would also have been motivated to consult Miyatake’s teachings to reduce the memory die size (Miyatake, paragraph [0106]). 36. With respect to claim 12, Miyatake discloses an apparatus where the first active material, the second active material, the third active material, and the fourth active material include an N-type active material (see paragraph [0080], “For example, an active region may include P+ diffusion material or N+ diffusion material to form p-channel type or n-channel type transistors, respectively”). Conclusion 37. All claims are identical to, patentably indistinct from, or have unity of invention with the claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571) 272-4179. The examiner can normally be reached on weekdays between 9:00 am to 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on 571-272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Woo H. Choi/ Primary Examiner, Art Unit 3992
Read full office action

Prosecution Timeline

Feb 14, 2024
Application Filed
Jul 29, 2025
Non-Final Rejection mailed — §102, §103, §112
Oct 27, 2025
Response Filed
Jan 16, 2026
Final Rejection mailed — §102, §103, §112
Mar 03, 2026
Response after Non-Final Action
Mar 10, 2026
Request for Continued Examination
Mar 11, 2026
Response after Non-Final Action
Sep 16, 2026
Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
84%
Grant Probability
79%
With Interview (-4.1%)
2y 11m (~4m remaining)
Median Time to Grant
High
PTA Risk
Based on 91 resolved cases by this examiner. Grant probability derived from career allowance rate.

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