DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7, 11-12, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hodono et al. (US 7995881 B2).
Re claim 1, Hodono et al. discloses a structure comprising: a first chip (W1) having a first surface, and including a first optical component (7; col. 11, lines 6-34) and an optical waveguide protrusion (7b/7y; figs. 1 & 6) adjacent to the first optical component, the optical waveguide protrusion extending above the first surface of the first chip (fig. 6); and a second chip (E) having a second surface (surface of 5) adjacent to the first surface of the first chip, the second chip including a second optical component (11/12) and a groove adjacent to the second optical component, the groove (4) extending from the second surface of the second chip and into a portion of the second chip (fig. 6), wherein the first surface of the first chip directly contacts the second surface of the second chip at a bonding interface (fig. 1), and wherein the optical waveguide protrusion (7b/7y) is positioned in the groove (4) in the second chip while the first and second surfaces are in direct contact (fig. 7; col. 5, lines 1-31 and col. 11, lines 6-34).
Re claim 2, Hodono et al. discloses the structure of claim 1, wherein the first optical component is a first optical waveguide (7; figs. 6-7) and the optical waveguide protrusion (7b) is a second optical waveguide (col. 5, lines 1-31) of the structure, the second optical waveguide is disposed on the first optical waveguide and abuts a portion of a top surface of the first optical waveguide (figs. 1 & 6).
Re claim 7, Hodono et al. discloses the structure of claim 1, wherein the first chip (W1) further includes a first dielectric layer (6; col. 5, lines 1-31) surrounding the first optical component, and the second chip (E) further includes a second dielectric layer (5) surrounding the groove (4; fig. 6), wherein the second dielectric layer directly contacts the first dielectric layer at the bonding interface (fig. 1).
Re claim 11, Hodono et al. discloses the structure of claim 1, wherein the optical waveguide protrusion partially fills the groove, and further comprising an air gap below the optical waveguide protrusion (fig. 1, there is a gap between 7b and the surface of 1; col. 8, lines 4-17).
Re claim 12, Hodono et al. discloses the structure of claim 1, further comprising a sealing material (epoxy) between the optical waveguide protrusion and the groove (col. 13, lines 31-44).
Re claim 19, Hodono et al. discloses a method (fig. 6; col. 11, lines 4-34), comprising: forming a first chip (W1; figs. 1 & 7) having a first surface (top surface of 6), and including a first optical component (7) and an optical waveguide protrusion (7b/7y) adjacent to the first optical component, the optical waveguide protrusion extending above the first surface of the first chip (fig. 6); forming a second chip (E) having a second surface (bottom surface of 5) and including a second optical component (12) and a groove (4) adjacent to the second optical component, the groove extending from the second surface of the second chip and into a portion of the second chip (fig. 6); positioning the optical waveguide protrusion in the groove in the second chip (fig. 1); and bonding the first surface of the first chip to the second surface of the second chip, wherein the first surface of the first chip directly contacts the second surface of the second chip at a bonding interface, and the optical waveguide protrusion is positioned in the groove in the second chip while the first and second surfaces are in direct contact (col. 5, lines 7-10).
Re claim 20, Hodono et al. discloses the method of claim 19, wherein forming the first chip further comprises patterning the optical waveguide protrusion using laser ablation (col. 10, lines 22-36).
Claim(s) 1, 10-12, 15, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mahgerefteh et al. (US 20160131837 A1).
Re claim 1, Mahgerefteh et al. discloses a structure (figs. 19-20) comprising: a first chip (704/2002) having a first surface, and including a first optical component (first 2006; [0159]) and an optical waveguide protrusion (730A/second 2006) adjacent to the first optical component, the optical waveguide protrusion extending above the first surface of the first chip (fig. 20); and a second chip (1700/2004) having a second surface adjacent to the first surface of the first chip, the second chip including a second optical component (1712) and a groove (1702/2008) adjacent to the second optical component, the groove extending from the second surface of the second chip and into a portion of the second chip (figs. 19-20), wherein the first surface of the first chip directly contacts the second surface of the second chip at a bonding interface (fig. 19B), and wherein the optical waveguide protrusion (730A/second 2006) is positioned in the groove (1702/2008) in the second chip while the first and second surfaces are in direct contact (figs. 19-20).
Re claim 10, Mahgerefteh et al. discloses the structure of claim 1, wherein the first optical component (first 2006) and the second optical component (1712) are optical waveguides ([0151] and [0159]), and the first optical component, the second optical component and the optical waveguide protrusion are formed of the same material (polymer [0154]).
Re claim 11, Mahgerefteh et al. discloses the structure of claim 1, wherein the optical waveguide protrusion partially fills the groove, and further comprising an air gap below the optical waveguide protrusion (close contact; [0157]).
Re claim 12, Mahgerefteh et al. discloses the structure of claim 1, further comprising a sealing material between the optical waveguide protrusion and the groove (epoxy underfill 1902; [0157]).
Re claim 15, Mahgerefteh et al. discloses the structure of claim 1, wherein the first chip (2102; fig. 21) further comprises an alignment structure (2110) extending above the first surface of the first chip, the second chip (2112) having a second groove extending below the second surface of the second chip, and wherein the alignment structure is positioned in the second groove in the second chip (fig. 21).
Re claim 19, Mahgerefteh et al. discloses a method, comprising: forming a first chip (2002) having a first surface, and including a first optical component (first 2006) and an optical waveguide protrusion (second 2006) adjacent to the first optical component, the optical waveguide protrusion extending above the first surface of the first chip (fig. 20); forming a second chip (2004) having a second surface and including a second optical component (1712 – figs. 19A-B for reference) and a groove (2008) adjacent to the second optical component, the groove extending from the second surface of the second chip and into a portion of the second chip (fig. 20); positioning the optical waveguide protrusion in the groove in the second chip (fig. 19B for reference); and bonding the first surface of the first chip to the second surface of the second chip, wherein the first surface of the first chip directly contacts the second surface of the second chip at a bonding interface, and the optical waveguide protrusion is positioned in the groove in the second chip while the first and second surfaces are in direct contact ([0059]).
Re claim 20, Mahgerefteh et al. discloses the method of claim 19, wherein forming the first chip further comprises patterning the optical waveguide protrusion using laser ablation ([0167]).
Claim(s) 1-5, 7-10, 12, and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aoki et al. (US 6236786 B1).
Re claim 1, Aoki et al. discloses a structure (figs. 1-2) comprising: a first chip having a first surface (bottom surface of top 7), and including a first optical component (top 7; col. 4, lines 4-27) and an optical waveguide protrusion (2) adjacent to the first optical component, the optical waveguide protrusion extending above the first surface of the first chip (figs. 1-2); and a second chip (substrate 1 and bottom 7) having a second surface (top surface of substrate 1) adjacent to the first surface of the first chip (figs. 1-2), the second chip including a second optical component (bottom 7) and a groove (3) adjacent to the second optical component, the groove extending from the second surface of the second chip and into a portion of the second chip, wherein the first surface of the first chip directly contacts the second surface of the second chip at a bonding interface, and wherein the optical waveguide protrusion is positioned in the groove in the second chip while the first and second surfaces are in direct contact (figs. 1-2; top surface of substrate 1 in direct contact with the bottom surface of top waveguide 7).
Re claim 2, Aoki et al. discloses the structure of claim 1, wherein the first optical component (top 7) is a first optical waveguide and the optical waveguide protrusion (2) is a second optical waveguide of the structure, the second optical waveguide is disposed on the first optical waveguide and abuts a portion of a top surface of the first optical waveguide (figs. 1-2).
Re claim 3, Aoki et al. discloses the structure of claim 2, wherein the second optical component (bottom 7) is a third optical waveguide of the structure, the third optical waveguide abuts the second optical waveguide (2; figs. 1-2).
Re claim 4, Hodono et al. discloses the structure of claim 3, wherein the third optical waveguide (bottom 7 or 23) is arranged laterally adjacent to the second optical waveguide (2/22; figs. 5, 8).
Re claim 5, Aoki et al. discloses the structure of claim 3, wherein the third optical waveguide is arranged over the second optical waveguide and a portion of the third optical waveguide overlaps the second optical waveguide (figs. 1-2).
Re claim 7, Aoki et al. discloses the structure of claim 1, wherein the first chip further includes a first dielectric layer (16; fig. 6; col. 5, lines 40-43) surrounding the first optical component (top 7), and the second chip further includes a second dielectric layer (1 made of polyimide; col. 3, lines 20-35) surrounding the groove (3), wherein the second dielectric layer directly contacts the first dielectric layer at the bonding interface (figs. 1-2).
Re claim 8, Aoki et al. discloses the structure of claim 7, wherein a top surface of the first dielectric layer (16) and the first optical component (top 7) is substantially coplanar (figs. 1-2 and 6), and the second dielectric layer (1) directly contacts at least a portion of the top surface of the first optical component (figs. 1-2).
Re claim 9, Aoki et al. discloses the structure of claim 1, wherein the first chip further comprises a first bond pad, and the second chip further comprises a second bond pad, the first chip is bonded to the second chip via the first bond pad and the second bond pad (col. 4, lines 20-27).
Re claim 10, Aoki et al. discloses the structure of claim 1, wherein the first optical component and the second optical component are optical waveguides, and the first optical component, the second optical component and the optical waveguide protrusion are formed of the same material (fluorine-contained polyimide resin; col. 3, line 61 through col. 4, line 9).
Re claim 12, Aoki et al. discloses the structure of claim 1, further comprising a sealing material between the optical waveguide protrusion and the groove (col. 3, line 54 through col. 4, line 3).
Re claim 16, Aoki et al. discloses a structure comprising: a first chip including a first optical waveguide (top 7), a second optical waveguide (2) arranged on the first optical waveguide, and a first dielectric layer (16; fig. 6; col. 5, lines 40-43) surrounding the first optical waveguide, wherein the second optical waveguide (2) extends above a top surface of the first dielectric layer (16); and a second chip (substrate 1 and bottom 7) stacked over the first chip, the second chip including a second dielectric layer (1) arranged over the first dielectric layer, a third optical waveguide (bottom 7) and a groove (3) adjacent to the third optical waveguide in the second dielectric layer, wherein the groove extends from a top surface of the second dielectric layer (1) and into the second dielectric layer, wherein the top surface of the first dielectric layer (16) of the first chip directly contacts the top surface of the second dielectric layer (1) of the second chip at a bonding interface (figs. 1-2; col. 4, lines 20-27), and wherein the second optical waveguide (2) is positioned in the groove (3) in the second chip while the top surface of the first dielectric layer and the top surface of the second dielectric layer are in direct contact (figs. 1-2).
Re claim 17, Aoki et al. discloses the structure of claim 16, wherein the second optical waveguide abuts the first optical waveguide and the third optical waveguide (figs. 1-2).
Re claim 18, Aoki et al. discloses the structure of claim 17, wherein the second optical waveguide (22) has a first side surface (vertical) adjoining a second side surface (20a) to form a corner of the second optical waveguide having an acute angle (fig. 8).
Re claim 19, Aoki et al. discloses a method, comprising: forming a first chip having a first surface (bottom surface of top 7), and including a first optical component (top 7) and an optical waveguide protrusion (2) adjacent to the first optical component, the optical waveguide protrusion extending above the first surface of the first chip (figs. 1-2); forming a second chip (substrate 1 and bottom 7) having a second surface (top surface of 1) and including a second optical component (bottom 7) and a groove (3) adjacent to the second optical component, the groove extending from the second surface of the second chip and into a portion of the second chip (figs. 1-2); positioning the optical waveguide protrusion in the groove in the second chip (figs. 1-2); and bonding the first surface of the first chip to the second surface of the second chip (col. 4, lines 20-27), wherein the first surface of the first chip directly contacts the second surface of the second chip at a bonding interface, and the optical waveguide protrusion is positioned in the groove in the second chip while the first and second surfaces are in direct contact (figs. 102).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hodono et al. (US 7995881 B2) in view of Witmer et al. (US 20230085761 A1).
Re claim 14, Hodono et al. discloses the structure of claim 1, but fails to teach the first chip further includes a second groove extending below the first surface of the first chip, and the second chip further includes a second optical waveguide protrusion extending above the second surface of the second chip, and wherein the second optical waveguide protrusion is positioned in the second groove in the first chip.
However, adding the same groove of the second chip to the first chip and adding the same optical waveguide protrusion of the first chip to the second chip is merely a duplication in parts as a design variation as evidenced by Witmer et al., in fig. 4, wherein the first chip (410) further includes a second groove (456) extending below the first surface of the first chip, and the second chip (420) further includes a second optical waveguide protrusion (424) extending above the second surface of the second chip, and wherein the second optical waveguide protrusion (424) is positioned in the second groove (456) in the first chip (410). Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to add another groove and waveguide protrusion as claimed since it has been held that the mere duplication of the essential working parts of a device involves only routine skill in the art, it would have been obvious before the effective filing date to a person having ordinary skill in the art to provide Hodono et al. with an alternative arrangement of the first optical element, i.e., on the other side of the opto-electric module. St Regis Paper Co v Bemis Co., 193 USPQ 8
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not disclose or render obvious the structure of claim 1, wherein the optical waveguide protrusion is an upper portion of a second optical waveguide, the second optical waveguide further comprises a lower portion extending below the first surface of the first chip, the second optical waveguide is laterally spaced from the first optical waveguide in the first chip, and the second optical waveguide forms a ring resonator.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dougherty et al. (US 20090324163 A1): claims 1, 2, and 10-12 (figs. 27 and 29)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Uyen-Chau N. Le whose telephone number is (571)272-2397. The examiner can normally be reached Monday-Friday, 9:00am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kiesha R. Bryant can be reached at (571) 272-3606. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/UYEN CHAU N LE/ Supervisory Patent Examiner, Art Unit 2874
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