DETAILED ACTION
This office action is in response to applicant’s amendments filed on 08/18/2026.
Currently claims 1-6, 9-11 and 13-16 are pending in the application.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been fully considered but are not persuasive. Applicant asserts that independent claim 1 has been amended to incorporate the indicated allowable features of claim 9. However, claim 9 was indicated allowable only if rewritten in independent form including all the limitations of the base claim and any intervening claims, i.e., including intervening claim 6. Amended claim 1 does not include the limitations of intervening claim 6 (the plurality of transistors arranged on an outer perimeter of the access array and the peripheral circuit block of the second structure), nor the limitation of claim 9 that the plurality of micro capacitors “is arranged to face the peripheral circuit block of the second structure.” Instead, amended claim 1 recites only “a plurality of micro capacitors arranged at a periphery of the capacitor array,” which is broader than the subject matter indicated allowable. As set forth in the rejection below, this limitation is taught by US 2006/0289932 A1 (Ahn). Applicant’s amendment necessitated the new ground of rejection.
Applicant’s arguments with respect to claim 11 have been fully considered and are persuasive. Claim 11 has been amended to incorporate the allowable subject matter of former claim 12. The rejection of claim 11 under 35 U.S.C. 103 has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0025541 A1 (Hu) and further in view of US 2006/0289932 A1 (Ahn).
Regarding claim 1, Hu discloses, a stack type semiconductor memory device comprising: a first structure (as annotated on Fig. 1C; [0045] – [0051]) comprising:
a first substrate (as annotated on Fig. 1C),
a capacitor array (106, capacitor; Fig. 1C; [0047]), and
a first bonding layer (142; bonding pad; Fig. 1C; [0049]), the first substrate having an upper surface (top) and a lower surface (bottom),
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the capacitor array (106) having a plurality of capacitors integrated on the upper surface of the first substrate (with broadest reasonable interpretation, it can be considered that it is integrated on the upper surface of the substrate), and
the first bonding layer (142) formed on the capacitor array (106) (Fig. 1C; [0049]); and
a second structure (as annotated on Fig. 1C; [0045] – [0051]) comprising:
a second substrate (as annotated on Fig. 1C),
an access array (104, plurality of transistors; Fig. 1C; [0045]), and
a second bonding layer (126; bonding pad; Fig. 1C; [0046]),
the second substrate having an upper surface (bottom) and a lower surface (top),
the access array (104) having a plurality of access transistors (as evident in Fig. 1C) integrated on the upper surface of the second substrate, and
the second bonding layer (126) is bonded to the first bonding layer (142) (Fig. 1C; [0046], [0049]).
But Hu fails to teach explicitly, the second bonding layer formed on the lower surface of the second substrate.
However, by flipping the second substrate upside down, the second bonding layer (126) could be formed on the lower surface of the second substrate (Fig. 1C; [0046]). In MPEP 2144.04 (VI) (C), it is stated that Rearrangement of Parts is held to be an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hu and MPEP 2144.04 (VI) (C), to form the second bonding layer on the lower surface of the second substrate and bonded to the first bonding layer. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0130] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Hu further fails to teach explicitly, a plurality of micro capacitors arranged at a periphery of the capacitor array, the capacitor array having the plurality of capacitors and the plurality of micro capacitors integrated on the upper surface of the first substrate, and the first bonding layer formed on the capacitor array and the plurality of micro capacitors.
However, in analogous art, Ahn discloses, a semiconductor memory device (400; Figs. 4 and 6; [0045], [0051]) comprising a capacitor array (plurality of cell capacitors 470 in cell array region A; Fig. 6; [0045]) and a plurality of micro capacitors (plurality of capacitors 402 of power decoupling capacitor C1; Figs. 4 and 6; [0041], [0053]) arranged at a periphery of the capacitor array (formed in peripheral circuit region B, outside cell array region A; Figs. 4 and 6; [0045]),
wherein the plurality of capacitors (470) and the plurality of micro capacitors (402) are integrated on the upper surface of the same substrate (460) (the bottom electrodes 404, 404a and the top electrodes 406, 406a of the decoupling capacitor C1 and the cell capacitors 470 are formed simultaneously at the same level over the substrate 460; Fig. 6; [0047] – [0049]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hu and Ahn before him/her, to modify the first structure of Hu to include a plurality of micro capacitors arranged at a periphery of the capacitor array (106) and integrated on the upper surface of the first substrate, as taught by Ahn, such that the first bonding layer (142, 146) of Hu, which is formed over the capacitor-side structure, is formed on the capacitor array and the plurality of micro capacitors, since such power decoupling capacitors filter noise existing in operating voltages such as the power supply voltage (VDD) and the ground voltage (VSS) (Ahn, [0003]), and since forming them simultaneously with the cell capacitors provides the decoupling capacitance without additional process steps (Ahn, [0047] – [0049]). Absent this important teaching in Hu, a person with ordinary skill in the art would be motivated to reach out to Ahn while forming a memory device of Hu.
Regarding claim 2, Hu discloses, the stack type semiconductor memory device of claim 1, wherein the first bonding layer comprises: a plurality of first bonding pads (multiple bonding pads 142) electrically connected to the plurality of capacitors (106), respectively; and
a first bonding insulation layer (146; dielectric layer; Fig. 1C; [0049]) configured to electrically isolate the first bonding pads (142) from each other.
Regarding claim 3, Hu discloses, the stack type semiconductor memory device of claim 2, wherein the second bonding layer comprises: a plurality of second bonding pads (126) hybrid-bonded (at the interface of S1 and S2, the dielectric layers 146 and 130 are also bonded on top of metal to metal bonding; Fig. 1C) to the first bonding pads (Fig. 1C; [0050]) and electrically connected to the access transistors (individual transistor 104), respectively; and
a second bonding insulation layer (130; dielectric layer; Fig. 1C; [0046]) hybrid-bonded to the first bonding insulation layer (146) and configured to electrically isolate the second bonding pads (126) from each other.
Regarding claim 4, Hu discloses, the stack type semiconductor memory device of claim 3, wherein the capacitor array has a size corresponding to a size of the access array (evident in Fig. 1C).
Regarding claim 5, Hu discloses, the stack type semiconductor memory device of claim 4, wherein the second structure further comprises an embedded electrode (128; conducting member; Fig. 1C; [0046]) in the second substrate to connect the access transistors (individual transistor 104) to the second bonding pads (126).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0025541 A1 (Hu) and US 2006/0289932 A1 (Ahn) as applied to claim 1 and further in view of US 2023/0178505 A1 (Lee).
Regarding claim 6, the combination of Hu and Ahn fails to teach explicitly, the stack type semiconductor memory device of claim 1, wherein the second structure further comprises:
a plurality of transistors arranged on an outer perimeter of the access array; and
a peripheral circuit block including a plurality of interconnections electrically connected to the transistors.
However, in analogous art, Lee discloses, the stack type semiconductor memory device of claim 3, wherein the second structure further comprises:
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a plurality of transistors (as evident in Fig. 3; [0053]) arranged on an outer perimeter (outside the core area) of the access array (CR1 and CR2; memory core regions; Fig. 3; [0054]); and
a peripheral circuit block (as annotated in Fig. 3; [0053]) including a plurality of interconnections (BP2c and BP1c; Fig. 3) electrically connected to the transistors (as annotated in Fig. 3; [0053]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hu, Ahn and Lee before him/her, to modify the teachings of a semiconductor memory device as taught by Hu and to include the teachings of peripheral transistor block as taught by Lee since peripheral circuits plays an important role in the operation of the memory by providing various controls and absent this important teaching in Hu, a person with ordinary skill in the art would be motivated to reach out to Lee while forming a memory device of Hu.
Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon rejected base claims but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 9, the closest prior art, US 2023/0025541 A1 (Hu), in conjunction with US 2023/0178505 A1 (Lee) and US 2006/0289932 A1 (Ahn), and in combination with the other claimed features, fails to disclose, “the stack type semiconductor memory device of claim 6, wherein the first structure further comprises a plurality of micro capacitors, wherein the plurality of micro capacitors is arranged to face the peripheral circuit block of the second structure”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claim 10 is also objected to due to its dependence on an objected base claim.
Claims 11 and 13-16 are allowed.
The following is the examiner’s statement of reasons of allowance.
Independent claim 11 is allowable because the closest prior art US Patent Pub # US 2023/0025541 A1 to Hu teaches,
a stack type semiconductor memory device comprising:
a first substrate (as annotated on Fig. 1C; [0045] – [0051]) including a plurality of cell capacitors (106, capacitor; Fig. 1C; [0047]); and
a second substrate (as annotated on Fig. 1C; [0045] – [0051]) including access transistors (104, plurality of transistors; Fig. 1C; [0045]),
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wherein at least one of the first substrate and the second substrate comprises a plurality of hybrid-bonding pads (at the interface of S1 and S2, the dielectric layers 146 and 130 are also bonded on top of metal to metal bonding; Fig. 1C) connected between the cell capacitors (106) and the access transistors (104) to form a memory cell array (Fig. 1C; [0046], [0049]).
Furthermore, US Patent Pub # US 2023/0178505 A1 to Lee teaches, the second substrate including a plurality of word lines (WL), a plurality of bit lines (BL) intersected with the word lines (WL) (Fig. 3; [0043]), and
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access transistors (TR) connected to intersected portions between the word lines (WL) and the bit lines (BL) (Fig. 1; [0023]),
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However, neither Hu nor any cited prior art, appear to explicitly disclose, in combination with the other claimed features, wherein the second substrate comprises a peripheral circuit block including a plurality of transistors and a plurality of interconnections connected to the word lines and the bit lines, wherein the peripheral circuit block is integrated on the second substrate where the access transistors, the word lines and the bit lines are integrated.
Examiner’s Note: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by “wherein the second substrate comprises a peripheral circuit block including a plurality of transistors and a plurality of interconnections connected to the word lines and the bit lines, wherein the peripheral circuit block is integrated on the second substrate where the access transistors, the word lines and the bit lines are integrated”. Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, the claim is deemed patentable over the prior arts.
Specifically, the aforementioned ‘wherein the second substrate comprises a peripheral circuit block including a plurality of transistors and a plurality of interconnections connected to the word lines and the bit lines, wherein the peripheral circuit block is integrated on the second substrate where the access transistors, the word lines and the bit lines are integrated,’ is material to the inventive concept of the application at hand to achieve reduced thermal damage to transistor characteristics and improved reliability by forming capacitors first under high-temperature conditions and then forming transistors/wiring after bonding.
Dependent claims 13-16 depend, directly or indirectly, on allowable independent claim 11. Therefore, claims 13-16 are also allowable.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2023/0307011 A1 (Hasegawa) - A semiconductor memory device is disclosed including a first chip, a second chip, and a multiple of bonding pads. The first chip has a multiple of memory pillars that penetrate a multiple of wiring layers in a first direction. The second chip is bonded to the first chip. The multiple bonding pads are provided at a bonding face between the first chip and the second chip. The multiple of bonding pads include a first bonding pad that electrically connects a first memory pillar among the multiple of memory pillars to one of a multiple of transistors, and a second bonding pad that neighbors the first bonding pad when seen from the first direction, and which electrically connects a second memory pillar among the multiple of memory pillars to one of the multiple of transistors. The second memory pillar does not neighbor the first memory pillar when seen from the first direction.
US 2023/0005855 A1 (Simsek-Ege) - A method of forming a microelectronic device is disclosed comprising forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry at least partially overlying the first semiconductive structure, first back-end-of-line (BEOL) structures over and in electrical communication with the control logic circuitry, and first isolation material covering the control logic circuitry and the first BEOL structures. A second microelectronic device structure is bonded over the first BEOL structures to form a first assembly. The first assembly is vertically inverted. A third microelectronic device structure comprising a second semiconductor structure is bonded over the vertically inverted first assembly to form a second assembly. Memory cells comprising portions of the second semiconductor structure are formed after forming the second assembly. Second BEOL structures are formed over the memory cells.
US 2020/0328188 A1 (Liu) - A semiconductor device is disclosed including a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
10/06/2026
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