Prosecution Insights
Last updated: October 04, 2026
Application No. 18/442,114

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §112
Filed
Feb 15, 2024
Priority
Sep 27, 2023 — TW 112137127
Examiner
KIM, JAY C
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hon Young Semiconductor Corporation
OA Round
2 (Final)
49%
Grant Probability
Moderate
3-4
OA Rounds
10m
Est. Remaining
71%
With Interview

Examiner Intelligence

Grants 49% of resolved cases
49%
Career Allowance Rate
430 granted / 872 resolved
-18.7% vs TC avg
Strong +22% interview lift
Without
With
+21.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
63 currently pending
Career history
929
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
40.8%
+0.8% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
43.7%
+3.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 872 resolved cases

Office Action

§112
DETAILED ACTION This Office Action is in response to Amendment filed September 1, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The amendment filed September 1, 2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: (a) the amended Fig. 5 filed September 1, 2026 is not based on Applicant’s original disclosure especially when no one of ordinary skill in the art would refer to the corrugated surface with a plurality of facets or microfacets shown in the amended Fig. 5 as “a lattice plane” as Applicant referred to the planar surface in the original disclosure, (b) in addition, Applicant did not enable one of ordinary skill in the art to achieve the multifaceted etched substrate shown in the amended claim 5, which requires a plurality of different etch rates at different locations of the substrate with a directional etching of the dry etching that Applicant originally disclosed, and (c) it has been well-known to one of ordinary skill in the art that a dry etching of a substate such as a SiC substrate Applicant originally disclosed results in a flat surface as shown in, for example, Fig. 1 of Zhuang et al. (“Microscale pattern etch of 4H-SiC by inductively coupled plasma,” Journal of Materials Science: Materials in Electronics 30 (2019) pp. 18788-18793), which shows a planar surface formed by a dry etching process as illustrated below, which is markedly different from the amended Fig. 5. Applicant is required to cancel the new matter in the reply to this Office Action. PNG media_image1.png 378 416 media_image1.png Greyscale Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 12-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention. (1) Regarding claim 12, Applicant originally disclosed in paragraph [0021] of current application that “Refer to FIG. 5, etching the substrate 110 with the developed photoresist 120′ such that a lattice plane 130 of the substrate 110 is exposed, in which the lattice plane 130 is parallel to the c-axis and is correspond to the (11-20) direction or the (1-100) direction (emphases added)”, in paragraph [0022] of current application that “Refer to FIG. 5 and FIG. 6, after etching the substrate 110 and exposing the lattice plane 130 parallel to the c-axis and correspond to the (11-20) direction or the (1-100) direction, growing an epitaxial layer 140 on the lattice plane 130 and the epitaxial layer 140 directly contact the lattice plane 130 (emphases added)”, and in paragraph [0025] of current application that “In summary, since a lattice plane 130 that is parallel to the c-axis and corresponds to the (11-20) direction or the (1-100) direction is formed using a photoresist 120′ with an included angle θ through the method of dry etching along the included angle θ of the photoresist 120′ before forming the transistor structure, when the epitaxial layer 140 grows thereafter, the epitaxial layer 140 can grow along the lattice plane 130 parallel to the c-axis (emphases added)”. However, Applicant did not originally disclose that the etched substrate whose “lattice plane of the substrate parallel to the c-axis is exposed” as recited on lines 9-10 of the amended claim 12 would look like the multifaceted substrate as shown in the amended Fig. 5 filed September 1, 2026 as Applicant argues in the REMARKS filed September 1, 2026, because (a) the original disclosure cited above appears to suggest that the claimed “lattice plane of the substrate” corresponds to the (11-20) direction or the (1-100) direction, neither of which is shown in the amended Fig. 5 filed September 1, 2026, (b) furthermore, the amended Fig. 5 does not appear to make any sense in that the originally filed Fig. 5 of current application should have been formed from the structure shown in the originally filed Fig. 4 of current application by etching along the top surface or side surface 121 of the developed photoresist 120’ as illustrated below, PNG media_image2.png 386 640 media_image2.png Greyscale PNG media_image3.png 340 636 media_image3.png Greyscale (c) however, the amended Fig. 5 illustrated below does not appear to make any sense physically since there is no reason that the bottommost facet is etched the fastest, while the surrounding facets are etched at a slower rate(s) when all the facets expose surfaces with the same orientations and when the circular area 110 in the amended Fig. 5 correspond to one of the regions marked by the slanted lines in Fig. 4, PNG media_image4.png 652 822 media_image4.png Greyscale (d) in other words, the aeras corresponding to the triangular shapes shown in Fig. 4 illustrated above would be uniformly exposed to the dry etching Applicant originally disclosed, and therefore, the etched areas of the substrate 110 should be more or less like the illustration below, PNG media_image5.png 382 648 media_image5.png Greyscale or should look like the originally filed Fig. 5 of current application, (e) in the former case or in the case of the etched substrate shown in the amended Fig. 5, there is no apparently good reason to pattern the photoresist 120 shown in Fig. 3 of current application to form the patterned photoresist 120’ with inclined side surfaces as shown in Fig. 4 of current application since the pattern of the patterned photoresist 120’ would not be transferred to the substrate 110, (e) therefore, it is clear that the amended Fig. 5 is incorrect and is with factual errors as well as potentially not being compliant with the Enablement Requirement since Applicants did not originally disclose to enable one of ordinary skill in the art to achieve the various etch rates in the regions of the substrate not covered by the patterned photoresist 120’ as indicated by the amended Fig. 5, (f) in this case, it is clear that the claimed invention recited in the amended claim 12 based on the multifaceted substrate illustrated in the amended Fig. 5 fails to comply with the written description requirement, and (g) furthermore, the amended Fig. 5 does not even reflect the original disclosure of the portions of paragraphs [0021], [0022] and [0025] of current application cited above mentioning that “a lattice plane 130” “corresponds to the (11-20) direction or the (1-100) direction” since the multiple facets shown in the amended Fig. 5 do not correspond to the (11-20) direction or the (1-100) direction. (2) Further regarding claim 12, if arguendo “a lattice plane of the substrate parallel to the c-axis” recited on lines 9-10 refers to the newly illustrated and alleged lattice plane 130 shown in the amended Fig. 5 filed September 1, 2026, then the limitation “growing an epitaxial layer on the lattice plane of the substrate such that the epitaxial layer is grown along the lattice plane parallel to the c-axis” recited on lines 11-12 would suggest that the epitaxial layer that is initially formed would look like the rectangular areas illustrated below, PNG media_image6.png 638 738 media_image6.png Greyscale (b) however, Applicant did not originally disclose such a lateral epitaxial layer growth on the lattice plane of the substrate parallel to the c-axis as recited on lines 11-12 since (i) Applicant did not originally disclose such a lateral epitaxial layer growth, and (ii) rather, the epitaxial layer growth shown in the illustration above would be impossible to achieve since the epitaxial layer growth would occur in the c-axis direction rather than in a direction perpendicular to the c-axis direction, and (c) this point is further substantiated in that Applicant further claims that “the epitaxial layer has a thickness in a range from 10 micrometers to 20 micrometers” in claim 19, which would suggest that the distances between the alleged lattice planes 130 on opposing sides of the etched substrate parallel to the c-axis should be greater than “10 micrometers to 20 micrometers”, which in turn would suggest that the distances between the neighboring portions of the patterned photoresist 120’ shown in Fig. 4 of current application are also greater than “10 micrometers to 20 micrometers”, which Applicants did not originally disclose, either. Claims 13-20 depend on claim 12, and therefore, claims 13-20 fail to comply with the written description requirement. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. (1) Regarding claim 12, it is not clear what the limitation “etching the substrate with the patterned photoresist such that a lattice plane of the substrate parallel to the c-axis is exposed” recited on lines 9-10 suggests, because (a) for “a lattice plane of the substrate parallel to the c-axis” to be “exposed”, the etching of the substrate with the patterned photoresist should be performed in a direction along the -c-axis shown in Fig. 3 of current application, especially in view of Fig. 2 of current application, since otherwise “a lattice plane of the substrate parallel to the c-axis” would not be “exposed”, (b) Applicant originally disclosed in paragraph [0018] of current application that “In Miller-Bravias indices, the four numbers in the brackets (such as the (11-20) lattice plane in the present disclosure) represents the reciprocal of the incident point of the lattice plane and the four axes a1, a2, a3 and c”, that “If a particular lattice plane is parallel to an axis, the incident point can be interpreted as the infinity, which is zero after taking the reciprocal”, that “Therefore, it can be understand that since the last index of the (11-20) lattice plane and the (1-100) lattice plane are both zero, the incident point of these lattice planes and the c-axis are both at the infinity, which means that the lattice planes are parallel to the c-axis”, (c) in addition, Applicant originally disclosed in paragraph [0021] of current application that “Refer to FIG. 5, etching the substrate 110 with the developed photoresist 120′ such that a lattice plane 130 of the substrate 110 is exposed, in which the lattice plane 130 is parallel to the c-axis and is correspond to the (11-20) direction or the (1-100) direction”, (d) however, as the first line of the previously attached Geometry of Design: A Workbook (2014) pp. 217-223 states that “The rules of parallelism: a line is parallel to a plane if the line is parallel to any line in the plane”, the lattice plane 130 shown in Fig. 5 of current application is not parallel to the c-axis of the substrate, which is illustrated below, (e) furthermore, the claimed “included angle”, which is the angle θ shown in Fig. 4 of current application, is an angle or an associated angle that the exposed lattice plane 130 shown in Fig. 5 of current application makes with respect to the c-axis of the substrate, and (f) therefore, it does not appear that “a lattice plane of the substrate parallel to the c-axis is exposed” has nothing to do with the plane 130 shown in Fig. 3 of current application. PNG media_image7.png 358 646 media_image7.png Greyscale (2) Also regarding claim 12, it is not clear how the step of “etching the patterned substrate with the patterned photoresist” can expose “a lattice plane of the substrate parallel to the c-axis” as recited on lines 9-10, because (a) Applicant originally disclosed as if the pattern of the patterned photoresist 120’ is transferred into the substrate as shown in Fig. 5 of current application, (b) however, there is no such mechanism in a real world where the pattern of the patterned photoresist 120’ can be transferred into the substrate, especially when Applicant originally disclosed employing a dry etching for the etching process as recited in claim 18 and as disclosed in paragraph [0021] of current application, where the dry etching is a highly directional etching process, (c) when one employs a dry etching as Applicant originally disclosed, the substrate would be patterned as illustrated below, and PNG media_image8.png 382 654 media_image8.png Greyscale (d) therefore, it appears that the limitation “etching the substrate with the patterned photoresist such that a lattice plane of the substrate parallel to the c-axis is exposed” recited on lines 9-10 is mere a thought process that cannot be realized in a real word, which renders claim 12 noncompliant with the Enablement requirement, or Applicant did not originally disclose and does not claim the etching process parameters for transferring the pattern of the patterned photoresist into the substrate, in which case, claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps, see MPEP § 2172.01, and the omitted steps are: the etching process parameters with which Applicant transferred the pattern of the patterned photoresist into the substrate pattern by using a highly directional etching process. (3) Further regarding claim 12, it is not clear what the limitation “growing an epitaxial layer on the lattice plane of the substrate such that the epitaxial layer is grown along the lattice plane parallel to the c-axis” recited on lines 11-12 suggests, because (a) “the plane parallel to the c-axis” refers to the lattice plane 130 shown in Fig. 5 of current application, and this lattice plane 130 is not exactly parallel to the c-axis, and the epitaxial layer refers to the epitaxial layer 140 shown in Fig. 6 of current application, (b) therefore, “the epitaxial layer” 140 is not “grown along the lattice plane parallel to the c-axis” 130 contrary to the limitation recited on lines 11-12, (c) in other words, Applicant originally disclosed that the epitaxial layer 140 shown in Fig. 6 of current application is formed on the corrugated surface with the claimed “lattice plane” 130 shown in Fig. 5 of current application as illustrated below, PNG media_image9.png 350 644 media_image9.png Greyscale . PNG media_image10.png 406 674 media_image10.png Greyscale (d) however, when one performs an epitaxial growth on the corrugated surface shown in Fig. 5 of current application, the resulting epitaxial layer should resemble the epitaxial layer 22 shown in Fig. 4 of Zhong et al. (KR 20080104148 A) as illustrated below, where the “semipolar oriented gallium nitride facets 12 and 14” shown in Fig. 3 of Zhong et al. correspond to the lattice plane 130 shown in Fig. 5 of current application, and PNG media_image11.png 328 360 media_image11.png Greyscale (e) therefore, it is not clear whether the claimed invention recited in claim 12 is directed to an actual method or an abstract idea that cannot be converted into a real method since (i) Applicant did not originally disclose how the claimed epitaxial layer 140 can be grown “along the lattice plane parallel to the c-axis” 130, and then has the flat top surface as shown in Fig. 6 of current application, and (ii) if the claimed transistor recited on line 11 is formed on the corrugated epitaxial layer, the corrugated epitaxial layer would function as a scatterer of charge carriers present in a channel layer or a drift layer, resulting in a much reduced mobility of charge carriers, deteriorating the performance of the claimed transistor. Claims 13-20 depend on claim 12, and therefore, claims 13-20 are also indefinite. Response to Arguments Applicant’s arguments with respect to claim 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The Examiner notes that, if arguendo Applicant’s arguments in the REMARKS field September 1, 2026 are correct, then the amended claim 12 fails to comply with the written description requirement as discussed above under 35 USC 112(a) rejections, and therefore, it is clear that Applicant’s arguments based on the amended Fig. 5 filed September 1, 2026 are not persuasive. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ji et al., “Filling 4H-SiC trench towards selective epitaxial growth by adding HCl to CVD process,” Applied Physics Express 8 (2015) 065502. Sung et al., “Vertical and bevel-structured SiC etching techniques incorporating different gas mixture plasmas for various microelectronic applications,” Scientific Reports 7 (2017) 3915. Hamelin et al., “Precision Deep Reactive Ion Etching of Monocrystalline 4H-SiCOI for Bulk Acoustic Wave Resonators with Ultra-Low Dissipation,” Journal of The Electrochemical Society 168 (2021) 017512. Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /J. K./Primary Examiner, Art Unit 2815 September 18, 2026
Read full office action

Prosecution Timeline

Feb 15, 2024
Application Filed
Jun 01, 2026
Non-Final Rejection mailed — §112
Sep 01, 2026
Response Filed
Sep 21, 2026
Final Rejection mailed — §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
49%
Grant Probability
71%
With Interview (+21.6%)
3y 6m (~10m remaining)
Median Time to Grant
Moderate
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