DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Claims 1-3, 5-9, and 12-21 are pending in the office action.
Claims 1-3, 5-9, 16, and 19 have been amended.
Claims 4,10, and 11 have been canceled.
Claim Objections
Claim 1 is objected to because of the following informalities:
As per claim 1:
line 11: replaces “the output” with -- the first signal output --.
line 13: replaces “output” with -- the second signal output --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3, 5-9, and 16-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claims 1, 5, 16, and 19: recited “a non-zero threshold voltage” which was described application disclosure. Hence, this limit/feature/phrase is failing to comply with the written description requirement.
Claims 2-3, 6-9, 17-18, and 20-21 also rejected because are depended directly or indirectly from claims 1, 5, 16, and 19, respectively.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-9, and 16-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, 5, 16, and 19: recited the limitations “a non-zero threshold voltage” as unclear what is “a non-zero threshold voltage” meant to the claimed invention without describe in the specification.
Claims 2-3, 6-9, 17-18, and 20-21 also rejected because are depended directly or indirectly from claims 1, 5, 16, and 19, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, and16-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over (U.S. Pat. 8,330,469) (see reproduction fig. 8 as below).
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As per claim 1: Miyamoto teaches an apparatus (see fig. 8, reproduction above), comprising:
a first comparator (fig. 8, COMP1 (box as SEN2) includes CMP1 and CMP2 (similar above) having inputs coupled to first battery terminal V6 of cell (C6) and second battery terminal V7 of cell (C6), a threshold terminal (fig. 8, Vref), and an output (fig. 8, 1st SGN), the comparator (fig. 8, COMP1) configurable to provide a first signal at its output (fig. 8, 1st SGN) indicative of whether a voltage between first and second battery cell terminals (fig. 8, first battery terminal V6 and second battery terminal V7 of the cell C5) exceed a non-zero threshold voltage at the threshold terminal (fig. 8, Vref input to CMP1 (+) and CMP2), col. 6, ll. 1-15 and fig. 8, LOG2 excess voltage detection);
a second comparator (fig. 8, COMP2 (box as SEN3) includes CMP1 and CMP2 (similar above) having inputs coupled to third battery terminal V7 of cell (C7) and fourth battery terminal V8 of cell (C7), a threshold terminal (fig. 8, Vref), and an output (fig. 8, 2nd SGN), the comparator (fig. 8, COMP2) configurable to provide a second signal at its output (fig. 8, 2nd SGN) indicative of whether a voltage between third and fourth battery cell terminals (fig. 8, third battery terminal V7 and fourth battery terminal V8 of the cell Cc7) exceed a non-zero threshold voltage at the threshold terminal (fig. 8, Vref input to CMP1 (+) and CMP2), col. 6, ll. 1-15 and fig. 8, LOG2 excess voltage detection);
processing circuitry having first and second inputs (fig. 8, LOG1 and/or LOG2, 1st SGN input and 2nd SGN input) and output (fig. 8, LOG1 and/or LOG2), the first input of the processing circuitry coupled to the output of the first comparator (Fig. 8, 1st SGN), and the second input of the processing circuitry coupled to the output of the second comparator (fig. 8, 2nd SGN).
Miyamoto teaches two small comparators CMP1 and CMP2 (fig. 8), while figure 11 show a big comparator IC101 (fig. 11, IC 101).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine two small comparators CMP1 and CMP2 into a big single comparator (for example fig. 11, IC101) that given the engineer able to select/choice type or size of comparator as available of the inventory without undue experimental (see In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device).
As per claim 3: Miyamoto teaches the apparatus claim 1, wherein the processing circuitry includes a logical AND gate having inputs coupled to the first and second inputs of the processing circuitry and a logic OR gate having input to the first and second input of the processing circuitry, each of the logical AND gate and the logical OR gate having respective output coupled to the output of the processing circuitry (fig. 8, modify OR gate in LOG1 by combine with one of its output inverter to become AND having input to the first and second inputs 1st SGN and 2nd SGN; and leave OR gate in LOG2 as is, having input to the first and second inputs 3rd SGN and 4th SGN. Both AND gate and OR have output (low and excess voltage detection)).
As per claim 2: Miyamoto teaches the apparatus claim 3, wherein a state of least one of the output of the logic OR gate or the output of the logical AND gate provides an indication of whether a fault condition exist (fig. 4A-4B, fig. 7, T23, fig. 11, col. 2, ll. 9-44, abnormal potential to detect disconnection, detect defects of excess voltage for detecting disconnect; col. 8, line 43 – col. 9, line 20, leak current; col. 9, ll. 35-48, detecting disconnect).
As per claim 5: Miyamoto teaches a method, comprising:
comparing a voltage across each battery cell of multiple battery cells with a non-zero threshold voltage (fig. 8, COMP1 compares first battery terminal V6 and second battery terminal V7 of the cell C5 with a non-zero threshold voltage at the threshold terminal Vref); and
responsive to the comparing, determining at least one of: whether a fault condition exists in any of the multiple battery cells, or a fault condition exists in processing circuitry that processes results of the comparing (fig. 4A-4B, fig. 7, T23, fig. 11, col. 2, ll. 9-44, abnormal potential to detect disconnection, detect defects of excess voltage for detecting disconnect; col. 8, line 43 – col. 9, line 20, leak current; col. 9, ll. 35-48, detecting disconnect).
As per claim 6: Miyamoto teaches the method of claim 5, wherein comparing a voltage across each battery cells of multiple cells with a threshold includes comparing the voltage across each battery cell of the multiple battery cells with threshold using multiple comparators (fig. 8, multiple battery cells C5-C8, each cell has voltage across to be compared with Vref), and the method further comprises processing output signal of the multiple comparators with the processing circuitry (fig. 8, multiple comparator SEN1-SEN4 and processing circuitry LOG1 and LOG2, such as IC2).
As per claim 16: Miyamoto teaches an apparatus, comprising:
a first comparator having first, second, and third inputs coupled to, respectively, first and second battery cell terminals and a non-zero voltage reference (fig. 8, as taking SEN 2 (COMP1) for example, includes CMP1 and CMP2 (similar above) having inputs coupled to first battery terminal V6 of cell (C6) and second battery terminal V7 of cell (C6), a threshold terminal (fig. 8, Vref)), and an output (fig. 8, 1st SGN);
a second comparator having first, second, and third inputs coupled to, respectively, third and fourth battery cell terminals and the non-zero voltage reference and an output (fig. 8, COMP2 (box as SEN3) includes CMP1 and CMP2 (similar above) having inputs coupled to third battery terminal V7 of cell (C7) and fourth battery terminal V8 of cell (C7), a threshold terminal (fig. 8, Vref), and an output (fig. 8, 2nd SGN), the comparator (fig. 8, COMP2) configurable to provide a second signal at its output (fig. 8, 2nd SGN) indicative of whether a voltage between third and fourth battery cell terminals (fig. 8, third battery terminal V7 and fourth battery terminal V8 of the cell Cc7) exceed a non-zero threshold voltage at the threshold terminal (fig. 8, Vref input to CMP1 (+) and CMP2), col. 6, ll. 1-15 and fig. 8, LOG2 excess voltage detection); and
a logic gate having an output (fig. 8, LOG1 and/or LOG2, include OR logic gate) and first and second inputs (fig. 8, LOG1 and/or LOG2, 1st SGN input and 2nd SGN input), wherein the first input of the logic gate is directly connected to the output of the first comparator (Fig. 8, 1st SGN), and the second input of the logic gate is directly connected to the output of the second comparator (fig. 8, 2nd SGN).
As per claim 17: Miyamoto teaches the apparatus of claim 16, wherein the logic gate is a logical AND gate (fig. 8, modify OR gate in LOG1 by combine with one of its output inverter to become AND having input to the first and second inputs 1st SGN and 2nd SGN).
As per claim 18: Miyamoto teaches the apparatus of claim 17, further comprising a logical OR gate having first and second inputs and an output, wherein the first input of the OR gate is directly connected to the output of the first comparator, and the second input of the OR gate is directly connected to the output of the second comparator (fig. 8, LOG2 includes logic OR gate, 3rd SGN and 4th SGN).
As per claim 19: Miyamoto teaches an apparatus, comprising:
a first comparator having first, second, and third inputs coupled to, respectively, first and second battery cell terminals and a non-zero voltage reference, and (fig. 8, as taking SEN 2 (COMP1) for example, includes CMP1 and CMP2 (similar above) having inputs coupled to first battery terminal V6 of cell (C6) and second battery terminal V7 of cell (C6), a threshold terminal (fig. 8, Vref)), and an output (fig. 8, 1st SGN);
a second comparator having first, second, and third inputs coupled to, respectively, third and fourth battery cell terminals and the non-zero voltage reference, and an output (fig. 8, COMP2 (box as SEN3) includes CMP1 and CMP2 (similar above) having inputs coupled to third battery terminal V7 of cell (C7) and fourth battery terminal V8 of cell (C7), a threshold terminal (fig. 8, Vref), and an output (fig. 8, 2nd SGN), the comparator (fig. 8, COMP2) configurable to provide a second signal at its output (fig. 8, 2nd SGN) indicative of whether a voltage between third and fourth battery cell terminals (fig. 8, third battery terminal V7 and fourth battery terminal V8 of the cell Cc7) exceed a non-zero threshold voltage at the threshold terminal (fig. 8, Vref input to CMP1 (+) and CMP2), col. 6, ll. 1-15 and fig. 8, LOG2 excess voltage detection);
a third comparator having first, second, and third inputs coupled to, respectively, fifth and sixth battery cell terminals and the non-zero voltage reference, and an output (as similar to SEN2 and SEN3 as first and second comparator, using SEN4 as third comparator); and
a logic gate having an output and first, second, and third inputs, wherein the first input of the logic gate is coupled to the output of the first comparator, the second input of the logic gate is coupled to the output of the second comparator, and the third input of the logic gate is coupled to the output of the third comparator (fig. 8, LOG1 and LOG2 includes logic OR gate having inputs from first, second, and third comparator).
As per claim 20: Miyamoto teaches the apparatus of claim 19, wherein the logic gate is a logical AND gate (fig. 8, modify OR gate in LOG1 by combine with one of its output inverter to become AND having input to the first and second inputs 1st SGN and 2nd SGN).
As per claim 21: Miyamoto teaches the apparatus of claim 20, further comprising a logical OR gate having first, second, and third inputs and an output, wherein the first input is coupled to the output of the first comparator, the second input is coupled to the output of the second comparator, and the third input is coupled to the output of the third comparator (fig. 8, LOG1 and LOG2 includes logic OR gate having inputs from first, second, and third comparator).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyamoto et al., (U.S. Pat. 8,330,469) in view of Izawa (U.S. Pub. 20180024198).
As per claim 7: Miyamoto teaches the method of claim 5, wherein comparing a voltage across each battery cells of multiple cells with a threshold (fig. 8, COMP1 compares first battery terminal V6 and second battery terminal V7 of the cell C5 with a non-zero threshold voltage at the threshold terminal Vref) includes connecting each battery cell of the multiple battery cells to comparator (see fig. 8, COMP1 and COMP2), and processing an output signal of the comparator for each battery cell with the processing circuitry (fig. 8, 1st and 2nd processing circuitries, LOG1 and LOG2)
Miyamoto does not teaches connecting each battery cell of the multiple battery cells to comparator using a multiplexer.
Izawa teaches connecting each battery cell of the multiple battery cells to comparator using a multiplexer (fig. 1, fig. 3, and fig. 6, battery cells, mux 11, comparator 13).
It would have been obvious to one of ordinary in the art at the time of the effective filling date of claimed invention to combine Izawa and Miyamoto to modify Miyamoto’s voltage monitoring apparatus using Izawa’s a battery monitoring system connecting each battery cell of the multiple battery cells to comparator using a multiplexer for selecting voltage values (voltage signal in a first route and voltage signal second route) to be measure with respective measuring circuits and comparator 13 for comparing output values from the respective measuring circuits that detects the presence/absence of disconnection of the input and failure of the multiplexer (Izawa’s, par. [0039] [0040]).
As per claim 8: Miyamoto and Izawa teach the method of claim 7, further comprising storing output signal of the comparator for each battery cell in a respective register of multiple register, and providing the stored output signal to the processing circuitry from the multiple register (Izawa, fig. 1, fig. 3, and fig. 6, control unit 14).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if claim 9 is rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach the combination of limitations recited claim 9, comprise: wherein the processing circuitry includes a logical AND gate and a logical OR gate; wherein whether the fault condition exists in any of the multiple battery cells is determined responsive to an output state of the AND gate; and wherein whether the fault condition exists in the processing circuitry is determined responsive to an output state of the OR gate
Claims 12-15 are allowed.
The following is an examiner’s statement of reasons for allowance: see the previous office action mailed on 02/13/2025.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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NGHIA M. DOAN
Primary Examiner
Art Unit 2851
/NGHIA M DOAN/ Primary Examiner, Art Unit 2851