DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/15/2024was filed after the mailing date of the non-final rejection on 4/9/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1 through 20 rejected
Present action: claims 1 through 20 rejected
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the portion of first spacer” in line 13. The antecedence of the limitation is ambiguous and unclear. The “first spacer” lacks an article adjective and therefore does not explicitly refer to the preceding “first spacer”. Further “the portion” seems to be refer to “a portion” recited in line 11, but that element related to “a shape of an L”. The applicant is advised to reword the element to clearly and distinctly convey the scope of the claim
Claim 11 recites “the portion of first spacer” in line 18. The antecedence of the limitation is ambiguous and unclear. The “first spacer” lacks an article adjective and therefore does not explicitly refer to the preceding “first spacer” in line 8.
Claim 18 recites “the portion of first spacer” in line 22. The antecedence of the limitation is ambiguous and unclear. The “first spacer” lacks an article adjective and therefore does not explicitly refer to the preceding “first spacer”. Further “the portion” seems to be refer to “a portion” recited in line 20, but that element related to “a shape of an L”. The applicant is advised to reword the element to clearly and distinctly convey the scope of the claim
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1 through 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu (US 2019/0259839) in view of Kim (US 2021/0328033)
Regarding claim 1.
Ryu teaches:
A gate structure (fig 21:600; [para 0260]), comprising:
a gate electrode (fig 21:107,108,310; [para 0170]) on a substrate (fig 1,21:101; [para 0056]),
the gate electrode (fig 21:107,108,410I,310; [para 0260]) including a lower portion (fig 21:107,108; [para 0260]) and an upper portion (fig 21:410I,310; [para 0260]) sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate (fig 1,21:101; [para 0056]);
a spacer structure (fig 21:106b,309; [para 0260]) including a second spacer (fig 21:309; [para 0260]) and a first spacer (fig 21:106B; [para 0260]) sequentially stacked in a second direction substantially parallel to the upper surface of the substrate (fig 1,21:101; [para 0056]) on a sidewall of the upper portion of the gate electrode (fig 21:107,108,410I,310; [para 0260]);
and a gate insulation pattern (fig 21:106A; [para 0260]) on a lower surface and a sidewall of the lower portion (fig 21:107,108; [para 0260]) of the gate electrode (fig 21:107,108,410I,310; [para 0260]) and an outer sidewall of the spacer structure (fig 21:106B,309; [para 0260]);
wherein a cross-section of the first spacer (fig 21:106B; [para 0260]) has a shape of an "L" (fig 21), a portion of the shape of the "L" of the first spacer (fig 21:106B; [para 0260]) is arranged between the second spacer (fig 21:309; [para 0260]) and the lower portion (fig 21:107,108; [para 0260]) of the gate electrode (fig 21:107,108,410I,310; [para 0260]), wherein the portion of first spacer (fig 21:106B; [para 0260]), the second spacer (fig 21:309; [para 0260]), overlap in the first direction, and wherein the second spacer (fig 21:309; [para 0260]) includes a material (fig 21:309; [para 0171]) that is configured to induce a dipole ([para 0264]).
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Ryu does not teach an interface of the first spacer and the gate insulation pattern.
Kim teaches:
wherein, along the first direction, a portion of the first spacer (fig 3:106u; [para 0049]) is arranged on the lower portion (fig 3:108; [para 0042,0131]) of the gate electrode (fig 3:LB,UB; [para 0042,0131]), wherein the portion of first spacer (fig 3:106u; [para 0049]),and the lower portion (fig 3:108; [para 0042,0131]) of the gate electrode (fig 3:LB,UB; [para 0042,0131]) overlap in the first direction, and
an interface of the first spacer (fig 3:106u; [para 0049]) and the gate insulation pattern (fig 3:106L,106E; [para 0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an interface between the first spacer and the gate dielectric in order to reduce gate induced drain leakage (paragraph 4).
Regarding claim 2.
Ryu in view of Kim teaches the gate structure of claim 1, further
Kim teaches:
the spacer structure (fig 3:106u; [para 0049]) contacts an edge of an upper surface of the lower portion (fig 3:LB; [para 0049]) of the gate electrode.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an interface between the first spacer and the gate dielectric in order to reduce gate induced drain leakage (paragraph 4).
Regarding claim 3.
Ryu in view of Kim teaches the gate structure of claim 1, further
Ryu teaches:
the second spacer (fig 21:309; [para 0260]) includes lanthanum oxide (LaO), magnesium oxide (MgO) or strontium oxide (SrO) ([para 0080,0081,0174]).
Regarding claim 4.
Ryu in view of Kim teaches the gate structure of claim 3, further
Ryu teaches:
the first spacer (fig 21:106b; [para 0260]) includes a high dielectric material or silicon nitride ([para 0066]).
Regarding claim 5.
Ryu in view of Kim teaches the gate structure of claim 4, further
Ryu teaches:
the high dielectric material includes hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AIO) or tantalum oxide (TaO) ([para 0066]).
Regarding claim 6.
Ryu in view of Kim teaches the gate structure of claim 1, further
Kim teaches:
an area of an upper surface of the lower portion (fig 3:LB; [para 0049]) of the gate electrode (fig 3:LB,UB; [para 0042,0131]) is greater than an area of a lower surface of the upper portion (fig 8D:UB; [para 0049]) of the gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a lower portion with a greater area than an upper gate portion in order to reduce gate induced drain leakage (paragraph 4).
Regarding claim 7.
Ryu in view of Kim teaches the gate structure of claim 6, further
Ryu teaches:
the gate electrode (fig 21:107,108410I,310; [para 0260]) includes a metal nitride or a metal ([para 0068,0070]).
Regarding claim 8.
Ryu in view of Kim teaches the gate structure of claim 7, further
Ryu teaches:
the metal nitride includes titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN), and the metal includes tungsten (W), aluminum (A1) or molybdenum (Mo) ([para 0068,0070]).
Regarding claim 9.
Ryu in view of Kim teaches the gate structure of claim 1, further
Ryu teaches:
a gate mask (fig 21:111; [para 0260]) on the gate electrode (fig 21:107,108,410310; [para 0260]) and the spacer structure (fig 21:106b; [para 0260]),
Kim teaches:
wherein the gate insulation pattern (fig 3:106L,106e; [para 0049]) is on a sidewall of the gate mask (fig 3:112; [para 0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the gate insulation pattern on the gate mask in order to reduce gate induced drain leakage (paragraph 4).
Regarding claim 10.
Ryu in view of Kim teaches the gate structure of claim 1, further
Ryu teaches:
the upper portion (fig 21:410I,310; [para 0260]) of the gate electrode and the lower portion (fig 21:107,108; [para 0260]) of the gate electrode include substantially a same material ([para 0070]).
Claim(s) 11 through 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu (US 2019/0259839) in view of Kim (US 2021/0328033)
Regarding claim 11.
Ryu teaches:
A gate structure (fig 21:600; [para 0260]), comprising:
a gate electrode (fig 21:107,108,410I,310; [para 0260]) on a substrate (fig 1,21:101; [para 0056]),
the gate electrode (fig 21:107,108,410I,310; [para 0260]) including a first conductive pattern (fig 21:107,108; [para 0260]) and a second conductive pattern (fig 21:410I,310; [para 0260]) sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate (fig 1,21:101; [para 0056]);
a spacer structure (fig 21:106b,309; [para 0260]) contacting a sidewall of the second conductive pattern (fig 21:310; [para 0260]) , the spacer structure (fig 21:106b,309; [para 0260])including a second spacer (fig 21:309; [para 0260]) and a first spacer (fig 21:106b; [para 0260]) sequentially stacked in a second direction substantially parallel to the upper surface of the substrate (fig 1,21:101; [para 0056])wherein, a portion of the first spacer (fig 21:106b; [para 0260])is arranged between the second spacer (fig 21:309; [para 0260])and the first conductive pattern (fig 21:107,108; [para 0260]) of the gate electrode (fig 21:107,108,410I,310; [para 0260]);
a gate insulation pattern (fig 21:106A; [para 0172]) on a lower surface and a sidewall of the first conductive pattern (fig 21:107,108; [para 0260]) ;
and a gate mask (fig 21:111; [para 0260]) contacting an upper surface of the second conductive pattern (fig 21:310; [para 0260]) and an upper surface of the spacer structure (fig 21:309; [para 0260]), wherein the upper surface of the spacer structure (fig 21:106b,309; [para 0260]), is substantially coplanar with the upper surface of the second conductive pattern (fig 21:310; [para 0260]), and wherein the first spacer (fig 21:106b; [para 0260]) includes a high dielectric material or silicon nitride ([para 0066]), and the second spacer (fig 21:309; [para 0260]) includes lanthanum oxide (LaO), magnesium oxide (MgO) or strontium oxide (SrO) ([para 0080,0081,0174]),and wherein the portion of first spacer (fig 21:106b; [para 0260]), the second spacer (fig 21:309; [para 0260]), overlap in the first direction.
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Ryu does not teach a gate insulation pattern on an outer sidewall of the spacer structure
Kim teaches:
a spacer structure (fig 3:106u; [para 0049]) contacting a sidewall of the second conductive pattern (fig 3:UB; [para 0049]) and an edge of an upper surface of the first conductive pattern (fig 3:LB; [para 0049]) the spacer structure including a first spacer (fig 3:106u; [para 0049])wherein, along the first direction, a portion of the first spacer (fig 3:106u; [para 0049]) is arranged on the first conductive pattern (fig 3:LB; [para 0049]) of the gate electrode (fig 3:LB,UB; [para 0042,0131]);
and wherein the portion of first spacer (fig 3:106u; [para 0049]), and the lower portion (fig 3:108; [para 0042,0131]) of the gate electrode (fig 3:LB,UB; [para 0042,0131]) overlap in the first directiona gate insulation pattern (fig 3:106L; [para 0049]) on a lower surface and a sidewall of the first conductive pattern (fig 3:LB; [para 0049]) and an outer sidewall of the spacer structure (fig 3:106U; [para 0049])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the gate insulation pattern on the gate mask in order to reduce gate induced drain leakage (paragraph 4).
Regarding claim 12.
Ryu in view of Kim teaches the gate structure of claim 11, further
Ryu teaches:
the high dielectric material includes hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AIO) or tantalum oxide (TaO) ([para 0066]).
Regarding claim 13.
Ryu in view of Kim teaches the gate structure of claim 11, further
Ryu teaches:
a cross-section of the first spacer (fig 21:106b; [para 0260]) has a shape of an "L".
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Regarding claim 14.
Ryu in view of Kim teaches the gate structure of claim 11, further
Ryu teaches:
each of the first (fig 21:107,108; [para 0260]) and second (fig 21:410I,310; [para 0260]) conductive patterns include a metal nitride or a metal ([para 0068,0070]).
Regarding claim 15.
Ryu in view of Kim teaches the gate structure of claim 11, further
Ryu teaches:
the metal nitride includes titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN), and the metal includes tungsten (W), aluminum (A1) or molybdenum (Mo) ([para 0068,0070]).
Regarding claim 16.
Ryu in view of Kim teaches the gate structure of claim 11, further
Ryu teaches:
the first (fig 21:107,108; [para 0260]) and second (fig 21:410I,310; [para 0260]) conductive patterns include substantially a same material ([para 0070]).
Regarding claim 17.
Ryu in view of Kim teaches the gate structure of claim 11, further
Ryu teaches:
the first (fig 21:107,108; [para 0260]) and second (fig 21:410I,310; [para 0260]) conductive patterns include different materials ([para 0070]).
Claim(s) 18 through 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu (US 2019/0259839) in view of Kim (US 2021/0328033) in view of Lim (US 2022/0077152)
Regarding claim 18.
Ryu teaches:
A semiconductor device (fig 21:600; [para 0260]) comprising:
an active pattern (fig 21:104; [para 0061]) on a substrate (fig 1,21:101; [para 0056]);
an isolation pattern (fig 21:103; [para 0059]) on a sidewall of the active pattern (fig 21:104; [para 00061]);
a gate structure (fig 21:600g; [para 0260]) extending in a first direction substantially parallel to an upper surface of the substrate (fig 1,21:101; [para 0056]) in upper portions of the active pattern (fig 21:104; [para 0061]) and the isolation pattern (fig 21:103; [para 0059]);
;
(fig 21:600g; [para 0260]) includes:
a gate electrode (fig 1,21:107,108,410I,310; [para 0260]) extending in the first direction, the gate electrode (fig 21:107,108,410I,310; [para 0260]) including a lower portion (fig 21:107,108; [para 0260]) and an upper portion (fig 21:410I,310; [para 0260]) sequentially stacked in a third direction substantially perpendicular to the upper surface of the substrate (fig 1,21:101; [para 0056]);
a spacer structure (fig 21:106b,309; [para 0260]) including a second spacer (fig 21:309; [para 0260]) and a first spacer (fig 21:106b; [para 0260]) sequentially stacked in the second direction on a sidewall of the upper portion (fig 21:410I,310; [para 0260]) of the gate electrode;
and a gate insulation pattern (fig 21:106a; [para 0172,0260]) on a lower surface and a sidewall of the lower portion (fig 21:107,108; [para 0260]) of the gate electrode ;
wherein a cross-section of the first spacer (fig 21:106b; [para 0260]) has a shape of an "L", wherein, a portion of the shape of the "L" of the first spacer (fig 21:106b; [para 0260]) is arranged between the second spacer (fig 21:309; [para 0260]) and the lower portion (fig 21:107,108; [para 0260]) of the gate electrode (fig 21:107,108,410I,310; [para 0260]), wherein the portion of first spacer (fig 21:106b; [para 0260]), the second spacer (fig 21:309; [para 0260]), overlap in the first direction, and wherein the second spacer (fig 21:309; [para 0264]) includes a material that is configured to induce a dipole ([para 0264]) .
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Ryu does not teach an interface between the first spacer and the gate insulation.
Kim teaches:
a bit line structure (fig 9:BL; [para 0134]) on a central portion of the active pattern (fig 9:104; [para 0022]), the bit line structure (fig 9:BL; [para 0134]) extending in a second direction substantially parallel to the upper surface of the substrate (fig 9,101; [para 0024]) and substantially perpendicular to the first direction (fig 1,9; [para 0134]);
and a capacitor structure (fig 9:CAP; [para 0137]) and a gate insulation pattern (fig 9:106L; [para 0135]) on a lower surface and a sidewall of the lower portion (fig 9:108,109; [para 0135]) of the gate electrode (fig 0:LB,UB; [para 0042,0131]) and an outer sidewall of the spacer structure (fig 9:106u; [para 0135]);
wherein the portion of first spacer (fig 9:106u; [para 0135]),and the lower portion (fig 0:LB; [para 0042,0131]) of the gate electrode (fig 0:LB,UB; [para 0042,0131])overlap in the first direction,
and an interface of the first spacer (fig 9:106u; [para 0135]) and the gate insulation pattern (fig 9:106L,106E; [para 0135]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an interface between the first spacer and the gate dielectric in order to reduce gate induced drain leakage (paragraph 4).
Ryu does not teach a contact plug connecting a capacitor to the active region
Lim teaches:
a contact plug structure (fig 27:705,735,755; [para 0166])on each of opposite end portions of the active pattern (fig 27:405; [para 0166])
and a capacitor structure (fig 27:840; [para 0166]) on the contact plug structure (fig 27:705,735,755; [para 0166])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a capacitor and contact plug connecting to active pattern in order for the capacitor to function as a storage node for the device thereby enabling the structure to retain memory and function as DRAM (Ryu paragraph 335-336)
Regarding claim 19.
Ryu in view of Kim in view of Lim the semiconductor device of claim 18, further
Kim teaches:
the spacer structure (fig 9:106u; [para 0135]) contacts each edge in the second direction of an upper surface of the lower portion (fig 9:109; [para 0135]) of the gate electrode.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an interface between the first spacer and the gate dielectric in order to reduce gate induced drain leakage (paragraph 4).
Regarding claim 20.
Ryu in view of Kim in view of Lim the semiconductor device of claim 18, further
Ryu teaches:
the first spacer (fig 21:106b; [para 0260]) includes a high dielectric material or silicon nitride ([para 0066]),
and the second spacer (fig 21:309; [para 0260]) includes lanthanum oxide (LaO), magnesium oxide (MgO) or strontium oxide (SrO) ([para 0080,0081,0174]).
Response to Arguments
Applicant's arguments filed 7/24/2026 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach that the L shape portion of the first spacer is between the second spacer and the lower portion of the gate electrode.
However, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Specifically, combining Ryu and Kim would result in the formation of the dipole inducing material being embedded into the first spacer resulting in the claimed invention
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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