DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 103 3
A. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over EP-0241046-A2 (“Satoh”). 3
B. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0066636 (“Wang”) in view of US 2005/0124097 (“Xiang”). 5
C. Claims 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0049165 (“Yasuda”) in view of Xiang. 7
VI. Pertinent Prior Art 11
Conclusion 11
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of species I, claims 1, 2, and 6, in the reply filed on 08/07/2026 is acknowledged.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over EP-0241046-A2 (“Satoh”).
All reference characters are shown in the figures of the EP publication, and all citations to text are in the machine language translation attached with this Office action.
With regard to claim 1 Satoh discloses, generally in Fig. 5 and paragraph [0028] of the machine language translation, unless otherwise noted,
1. (Original) A semiconductor device, comprising:
[1] a semiconductor substrate 50;
[2a] an insulating film 54 located on the semiconductor substrate 50,
[2b] a first recess 59 being formed in an upper surface of the insulating film 54;
[3a] a silicon film 60 located on the insulating film 54,
[3b] the silicon film 60 including an impurity [¶ 15; infra],
[3c] a second recess being formed in an upper surface of the silicon film 60 in a region directly above the first recess 59;
[4] a silicide layer 64 [i.e. platinum silicide] located on the silicon film 60, the silicide 64 layer contacting the silicon film 60; and
[5a] a first contact 68 and a second contact 69 connected to portions of the silicide layer 64,
[5b] a region directly above the second recess being interposed between the portions [as shown in Fig. 5].
With regard to feature [3b] of claim 1, Satoh does not state that the polysilicon layer that forms the fuse 60 is doped with an impurity. However, Satoh explains that the polysilicon from which the fuse 11 is doped,
[0015] Referring to Fig. 1F, the transistor formation portion 1A is covered with a gate film 9 of silicon oxide having a thickness of 500 Å and formed by thermal oxidation. A polycrystalline silicon layer is then deposited over the entire surface and doped with phosphorus as an N-type impurity. The doped polycrystalline silicon layer is selectively removed to form, a gate electrode 10 of a MOS (Metal-Oxide-Silicon) transistor on the gate film 9 and a fuse film 11 on the thick field insulator layer 4 around the hollow 8. Thus, the doped polycrystalline layer is employed as a fusible conductive layer for the fuse 11 as well as the gate electrode 10. The fuse 11 is elongated in a widthwise direction of the hollow 8 to run across the hollow 8.
(Satoh: ¶ 15; emphasis added)
Moreover, Satoh states that the end portion 61 of the polysilicon layer from which the fuse 60 is made functions as the emitter electrode, which cannot happen if the polysilicon layer is not doped with sufficient impurity to make it conductive.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dope the entire polysilicon layer form which the fuse 60 is made because Satoh teaches that the fuse is made from doped polysilicon (¶ 15) and the same polysilicon layer must also be sufficiently conductive to function as the emitter electrode 61, as explained in Satoh (¶ 28).
This is all of the limitations of claim 1.
B. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0066636 (“Wang”) in view of US 2005/0124097 (“Xiang”).
Claim 1 reads,
1. (Original) A semiconductor device, comprising:
[1] a semiconductor substrate;
[2a] an insulating film located on the semiconductor substrate,
[2b] a first recess being formed in an upper surface of the insulating film;
[3a] a silicon film located on the insulating film,
[3b] the silicon film including an impurity,
[3c] a second recess being formed in an upper surface of the silicon film in a region directly above the first recess;
[4] a silicide layer located on the silicon film, the silicide layer contacting the silicon film; and
[5a] a first contact and a second contact connected to portions of the silicide layer,
[5b] a region directly above the second recess being interposed between the portions.
With regard to claim 1, Wang discloses, generally in Figs. 4A-4E,
1. (Original) A semiconductor device, comprising:
[1] a semiconductor substrate 101 [¶ 48];
[2a] an insulating film 102 [¶ 90] located on the semiconductor substrate 101,
[2b] a first recess being formed in an upper surface of the insulating film 102 [first recess is shown in each of Figs. 4B-4E but not labeled];
[3a] a silicon film 104 [¶ 90] located on the insulating film 102,
[3b] … [not taught] …
[3c] a second recess being formed in an upper surface of the silicon film 104 in a region directly above the first recess [again, not labeled, but best shown in Fig. 4D];
[4] a silicide layer 105 [¶ 90] located on the silicon film 104, the silicide layer 105 contacting the silicon film 104; and
[5a] a first contact 106 and a second contact 106 connected to portions of the silicide layer 105 [¶ 95],
[5b] a region directly above the second recess being interposed between the portions [as shown in Figs. 4D].
With regard to feature [3b] of claim 1,
[3b] the silicon film including an impurity,
Xiang, like Wang, teaches an e-fuse (e.g. Figs. 3 and 4) including a laminate of polysilicon 46 and metal silicide 48 (Xiang: ¶¶ 33-34) formed on a field oxide 44 that may also be LOCOS (Xiang: ¶¶ 28-29; Wang: ¶ 64). Xiang further teaches that the polysilicon layer 46 may be doped or undoped (Xiang: “Layer 46 can be a doped or undoped polysilicon layer.” [¶ 33]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dope the polysilicon layer 104 of Wang with impurity because Xiang teaches that each of doped and undoped polysilicon are suitable for the silicon layer of an e-fuse. As such, the selection of doped versus undoped polysilicon is a matter of obvious material choice. (See MPEP 2144.07.)
C. Claims 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0049165 (“Yasuda”) in view of Xiang.
Claim 1 reads,
1. (Original) A semiconductor device, comprising:
[1] a semiconductor substrate;
[2a] an insulating film located on the semiconductor substrate,
[2b] a first recess being formed in an upper surface of the insulating film;
[3a] a silicon film located on the insulating film,
[3b] the silicon film including an impurity,
[3c] a second recess being formed in an upper surface of the silicon film in a region directly above the first recess;
[4] a silicide layer located on the silicon film, the silicide layer contacting the silicon film; and
[5a] a first contact and a second contact connected to portions of the silicide layer,
[5b] a region directly above the second recess being interposed between the portions.
With regard to claim 1, Yasuda discloses, generally in Fig. 6,
1. (Original) A semiconductor device 40 [including “fuse element 11” (¶¶ 38-39)], comprising:
[1] a semiconductor substrate 51 [¶ 39];
[2a] an insulating film 55, 61 [¶¶ 41, 48] located on the semiconductor substrate 51,
[2b] a first recess [generally at 61] being formed in an upper surface of the insulating film 55, 61;
[3a] a silicon film 62 [¶ 41] located on the insulating film 55, 61,
[3b] … [not taught] …
[3c] a second recess [generally above 61] being formed in an upper surface of the silicon film 62 in a region directly above the first recess [generally at 61];
[4] a silicide layer located on the silicon film, the silicide layer contacting the silicon film; and
[5a] a first contact 68 and a second contact 68 connected to portions of the …[polysilicon layer 62]… layer,
[5b] a region directly above the second recess being interposed between the portions.
With regard to features [3b], [4], and [5a] of claim 1,
[3b] the silicon film including an impurity,
[4] a silicide layer located on the silicon film, the silicide layer contacting the silicon film; and
[5a] a first contact and a second contact connected to portions of the silicide layer,
Yasuda does not teach that (1) the polysilicon layer 62 includes an impurity, (2) a silicide is formed over the polysilicon 62, or (3) that the first 68 and second 68 contacts contact said silicide.
Xiang, like Yasuda, teaches an e-fuse (e.g. Figs. 3 and 4) including a laminate of polysilicon layer 46 formed on a field oxide 44 that may also be LOCOS (Xiang: ¶¶ 28-29; Yasuda: ¶¶ 39, 48). Xiang further teaches that the polysilicon layer 46 may be doped or undoped (Xiang: “Layer 46 can be a doped or undoped polysilicon layer.” [¶ 33]). Xiang also teaches that the upper surface of the polysilicon layer 46 is silicided by reaction with metal to form metal silicide 48 (Xiang: ¶ 34) and that the contacts 22, 24 contact the silicide 48 (Xiang: ¶ 32. Figs. 3, 4).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dope the polysilicon layer 62 of Yasuda with impurity because Xiang teaches that each of doped and undoped polysilicon are suitable for the silicon layer of an e-fuse. As such, the selection of doped versus undoped polysilicon is a matter of obvious material choice. (See MPEP 2144.07.)
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to silicide the upper surface of the polysilicon layer 62 of Yasuda, thereby having the contacts 68 contacting the silicide layer, because Xiang teaches that a silicided polysilicon layer is a known, suitable laminate for forming an e-fuse. (See MPEP 2143.)
This is all of the limitations of claim 1.
With regard to claim 2, Yasuda further discloses,
2. (Original) The device according to claim 1, wherein the insulating film includes:
[1] a first LOCOS film [55 below left portion of polysilicon layer 62 in Fig. 6]; and
[2] a second LOCOS film [55 below right portion of polysilicon layer 62 in Fig. 6],
[3] the first LOCOS film [left 55] and the second LOCOS film [right 55] are connected to each other [by oxide 61], and
[4] the first recess is at a connection portion 61 between the first LOCOS film [left 55] and the second LOCOS film [right 55].
With regard to claim 6, Yasuda modified by Xiang, as explained above, further teaches,
6. (Original) A method for manufacturing a semiconductor device, the method comprising:
[1] forming a first LOCOS film [55 below left portion of polysilicon layer 62 in Fig. 6] and a second LOCOS film [55 below left portion of polysilicon layer 62 in Fig. 6] at an upper surface of a semiconductor substrate 51 so that the first LOCOS film [left 55] and the second LOCOS film [right 55] are connected to each other [by thermal oxide 61; see Figs. 7A-7D; ¶ 48];
[2a] forming a silicon film 62(74) on a region including a connection portion 61 between the first LOCOS film [left 55] and the second LOCOS film [right 55] [¶ 49; Fig. 7E and 8A],
[2b] the silicon film 62(74) including an impurity [as taught in Xiang, supra];
[3] forming a silicide layer [e.g. 48 of Xiang used in Yasuda (supra and infra)] at an upper surface of the silicon film 62; and
[4] connecting a first contact 68 and a second contact 68 to regions of the silicide layer [of Yasuda/Xiang (supra and infra)],
[5] a region directly above the connection portion 61 being interposed between the regions of the silicide layer [of Yasuda/Xiang (supra and infra)].
With regard to features [3]-[5] of claim 6, note that Yasuda forms silicide layers 56c, 57c, 59a while the polysilicon layer 62 of the e-fuse 11 is formed, as shown in Fig. 8B of Yasuda (Yasuda: ¶ 50). As such, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to silicide the upper surface of the polysilicon layer 62 to form the silicided upper surface, taught by Xiang (supra), during the silicidation of the source, drain, and gate regions to form the silicide layers 56c, 57c, 59a, because Xiang teaches that a silicided polysilicon layer is a known, suitable laminate for forming an e-fuse and because it would consolidate the process steps from two separate silicidation steps into one, which would reduce the thermal budget of the process. So done, the contact 68 of Yasuda to the e-fuse 11 would contact the silicide layer of Yasuda/Xiang.
This is all of the limitations of claim 6.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2013/0105895 (“Liang”) is cited for disclosing each of the limitations of claim 1 except for the second recess being directly above the first recess. See at least Figs. 1A-1B, 2A-2B, 3A-3B and the associated text.
US 2008/0237786 (“Yang”) is cited for disclosing each of the limitations of claim 1 except for the first and second contacts. See Fig. 9B and the associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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