DETAILED ACTION
1. Claims 20-43 were pending in this divisional application of reissue application 17/529,490 for reissue of US Patent 10,482,033 (hereinafter “the ‘033 patent”). Original claims 1-19 have been cancelled. Claims 20-43 are new in this reissue application. This Office Action is responsive to amendments filed on December 18, 2025, in response (“the Response”) to the Office Action issued on October 21, 2025, and Request for Continued Examination (RCE) filed on January 20, 2026. In the Response, Applicant amended claims 20, 23-27, 34, 38, and cancelled claims 39-43. Claims 20-38 are currently pending.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior or Concurrent Proceedings
3. Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceed-ing in which the ‘033 patent is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation.
Information Material to Patentability
4. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is mate-rial to patentability of the claims under consideration in this reissue appli-cation.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Response to Amendments and Arguments
Rejections Under 35 USC 251 & 112
5. Claims have been amended or cancelled to overcome rejections under 35 USC 251 and 112. Corresponding rejections are withdrawn.
Rejections Under 35 USC 251 & 112
6. Applicant asserts that Le is not prior art because the priority date of the present application is March 24, 2016, which is earlier than Le’s filing data of June 24, 2016. Applicant acknowledges that Le claims priority to a provisional application filed on January 21, 2026 but argues that the provisional application does not appear to support the concept of determining a read source based on load-balancing criteria such as bandwidth. Shown below is the portion of the provisional application 62/312,670 filed on March 24, 2016 (“the ‘670 provisional application). The provisional application admits that the structure used for balancing dispatch is a prior art structure. This appears to be an admission that the claimed apparatus is a structure known in the art. Also, there’s no discussion any cache or bandwidths. By Applicant’s own argument against the provisional application of Le, a lack of disclosure of a bandwidth based load-balancing appears to rebut Applicant’s argument of priority claim.
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Applicant’s argument that Le is not prior art is not persuasive because claims are not supported by the disclosure in the ‘670 provisional application.
The examiner also notes that contrary to Applicant’s argument that Le’s provisional application does not appear to support the concept of determining a read source based on load-balancing criteria such as bandwidths, Le’s provisional application 62/281,234 specifically discloses in paragraph [0033] “ … Accordingly, the load balancing circuit 126 of the DRAM cache management circuit 102 determined from which source to read the data based on load balancing criteria such as bandwidth and latency, as non-limiting examples. …”
7. Applicant argues that Le does not disclose or suggest comparison between bandwidth of the cache and the bandwidth of the non-volatile memory. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant further argues that because Boehm addresses problem of inefficiency and high latency associated with flush operation in NVM system and Le provides DRAM cache management circuit that manages access between DRAM cache in a high-bandwidth memory system and DRAM, there’s no reason to combine the teachings. This is not a persuasive argument because Boehm’s teaching of cache flush operation in not the teaching that combined with Le’s load balancing teaching. It is Boehm’s disclosure that non-volatile memory is known in the art that is the main reason for the combination.
Claim Objection - 37 C.F.R. 1.173
8. 37 CFR 1.173 (g) states:
g) Amendments made relative to the patent. All amendments must be made relative to the patent specification, including the claims, and drawings, which are in effect as of the date of filing of the reissue application.
Claim amendments are objected to because amendments were not made relative to the patent claims which were in effect as of the date of filing of the reissue application. Amendments to new claims were made relative to the claims presented on February 15, 2024. Appropriate correction is required.
Claim Rejections - 35 USC § 112
9. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
10. Claims 35-37 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
11. With respect to claim 35, the claim requires accessing “the data” by using the cache and the memory. However, the specification does not describe accessing “the data” by using both the cache and the memory.
12. With respect to claim 36, the claim recites “determining whether to access the data by using the cache and the memory.” There’s no written description support for determining whether to access the data by using both the cache and the memory.
13. With respect to claim 37, the claim recites that limitation “wherein the accessing the data based on the first bandwidth and the second bandwidth includes accessing data based on a ratio between the first bandwidth and the second bandwidth.” There’s no written description support for the limitation “accessing data based on a ratio between the first bandwidth and the second bandwidth.”
14. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
15. Claims 34-37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 34 recites the limitation “the non-volatile memory” in line 13. There is insufficient antecedent basis for this limitation in the claim. Dependent claims 35-37 are rejected for the same reason.
Claim Rejections - 35 USC § 102
16. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
17. Claims 20-33 and 38 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Admitted Prior Art (‘APA”).
Following disclosures are from the ‘670 provisional application.
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With respect to apparatus claims 20-33 and 38, Applicant admitted that the structure used in the balancing dispatch is a prior art structure.
18. Claims 20-29, 31, and 33 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by US 2017/021280 (“Le”).
19. With respect to claim 20, Le discloses an apparatus comprising a memory controller (FIG. 1, 100) configured to:
receive a request for reading data of a memory (FIG. 3A, step 300);
determine whether to perform the request by utilizing a cache and the memory (FIG. 3A, 314) based on a comparison between first bandwidth and a second bandwidth, wherein the first bandwidth is the bandwidth of the cache and the second bandwidth is the bandwidth of the memory (paragraph [0029], “In circumstances in which a requested memory address can be read from either the system memory DRAM 110 or the DRAM cache 104, the load balancing circuit 152 determines the most appropriate source from which to read the memory address, based on load balancing criteria such as bandwidth and latency, as non-limiting examples.”).
20. With respect to claims 21 and 22, the examiner takes Official Notice that cache and main memories can store pages.
21. With respect to claim 23, Le discloses the apparatus of claim 20, wherein the request is performed by utilizing the cache (FIG. 3A, 318).
19. With respect to claim 24, Le discloses the apparatus of claim 20, wherein the request is performed by utilizing the memory (FIG. 3A, 316).
22. With respect to claim 25, Le discloses the apparatus of claim 20, wherein the cache and the memory are parts of a same memory device (see FIG. 1).
23. With respect to claim 26, Le discloses the apparatus of claim 20, wherein the cache and the memory are accessed based on the first bandwidth and the second bandwidth (see paragraph [0029]).
23. With respect to claim 27, Le discloses the apparatus of claim 20, wherein the cache and the memory are accessed based on a utilization rate of the first bandwidth and the second bandwidth (see paragraph [0029]).
24. With respect to claim 28, Le discloses the apparatus of claim 20, wherein the cache is s high-speed storage device (see paragraph [0005]).
25. With respect to claim 29, Le discloses the apparatus of claim 20, wherein the cache has a wider bandwidth than the memory, and has a smaller capacity that the memory (see paragraphs [0005]-[0006]).
26. With respect to claim 31, Le discloses the apparatus of claim 20, wherein the memory is a dynamic random access memory (DRAM) (see paragraph [0005]).
27. With respect to claim 33, Le discloses the apparatus of claim 20, wherein the cache is a dynamic random access memory (DRAM) (see paragraph [0005]).
Claim Rejections - 35 USC § 103
28. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
29. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
30. Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over US 2017/021280 (“Le”) in view of US Pat. 10,146,616 (“Shilane”).
Le discloses all of the limitations of the parent claim 20 as discussed above. However, Le does not specifically disclose using flash memory for cache. On the other hand, Shilane discloses that flash caches are a common component of storage systems (see Shilane, 1:26-29). It would have been obvious to use Le’s load balancing teachings in the storage system of Shilane to improve performance of the storage system (see Le, paragraph [0008]). Applying a known technique (i.e., Le’s load-balancing) to a known device (Shilane’s storage system) ready for improvement to yield predictable results is obvious under KSR vs. Teleflex.
31. Claims 30, 34 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/021280 (“Le”) in view of US 2016/0246724 (“Boehm”).
32. With respect to claim 34, Le discloses a method comprising:
receiving a request for reading data of a memory (FIG. 3A, step 300);
determining whether to perform the request by utilizing a cache and the memory (FIG. 3A, 314) based on first bandwidth corresponding to the cache and a second bandwidth corresponding to the memory (paragraph [0029], “In circumstances in which a requested memory address can be read from either the system memory DRAM 110 or the DRAM cache 104, the load balancing circuit 152 determines the most appropriate source from which to read the memory address, based on load balancing criteria such as bandwidth and latency, as non-limiting examples.”)
in response to a determination of accessing data by directly communicating with the cache, accessing the data by communicating with the cache (FIG. 3A, 318),
in response to a determination of accessing data by directly communicating with the [non-volatile] memory, accessing the data by communicating with the [non-volatile] memory (FIG. 3A, 316).
However, Le does not specifically disclose that the memory is non-volatile (the limitation indicated above in square brackets). On the other hand, Boehm discloses a system with a cache and a non-volatile system memory (Boehm, FIG. 1, 150) with a cache controller for non-volatile memory (see Title). It would have been obvious to one or ordinary skill in the art to use non-volatile memory as taught by Boehm in a computer system to be able to maintain data when not powered.
33. With respect to claims 30 and 38, see the rejection of claim 34 above.
Conclusion
34. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Woo H. Choi/
Primary Examiner, Art Unit 3992
Conferees:
/Cameron Saadat/Primary Examiner, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992
Prosecution Insights