DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
This Office Action is in response to 02/19/2026 Amendment and 03/06/2026 RCE.
Claims 1-3, 6, 8-17, 19-20 are pending and examined. Claims 4-5, 7, 18 have been cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 1-3, 9-10, 14, 17, 20 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by US 7,920,420 to Lee (hereafter Lee) with support from US 6,335,881 to Kim et al. (hereafter Kim).
Regarding independent claim 1, Lee teaches a memory device, comprising: control circuitry configured to:
program (FIGS 6-7: programming states 202 and 204 corresponding to of 1st Group 200), via a number of pulses in a first programming voltage range (FIG. 8: voltage range corresponding to 1st Group), a first number of memory cells to a level greater than or equal to a first particular level (FIG. 6: states 202 and 204 are greater than state 201);
load a second number of memory cells with level 0 data to inhibit programming of the second number of memory cells while the first number of memory cells is programmed (FIG. 6: i.e. inhibiting programming of states 231-201, see 7:35-8:41. Kim provides support that each of the bit lines of unselected group of memory cells is applied with Vcc by loading data “0” in a latch of the corresponding page buffer, see 2:9-12 and 5:39-43);
program (FIGS 6-7: programming states 212 and 214 of 2nd Group 210), via a number of pulses in a second, different programming voltage range (FIG. 8: voltage range corresponding to 2nd Group), the second number of memory cells to a level less than a second particular level (FIG. 6: states 212 and 214 are less than state 202), wherein the second particular level is greater than the first particular level (FIG. 6: state 202 is greater than state 201) and a start programming voltage of the first programming voltage range is substantially equal to a stop programming voltage of the second, different programming voltage range (see annotated FIG. 8 below); and
inhibit programming of the first number of memory cells while the second number of memory cells is programmed (FIG. 6: i.e. inhibiting programming of states 231-211 and 201-204, see 7:35-8:41).
Annotated FIG. 8 of Lee
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Regarding dependent claim 2, Lee teaches the control circuit further configured to: load data to be programmed to the first number of cells prior to programming the first number of cells; and load data to be programmed to the second number of memory cells prior to programming the second number of cells (because a select operation of the group units is repeated, see 8:20-41).
Regarding dependent claim 3, Lee teaches load inhibit level data to the first number of cells prior to programming the second number of cells (because a select operation of the group units is repeated, see 8:20-41).
Regarding dependent claim 9, Lee teaches wherein the control circuitry is configured to load the first number of memory cells with level 0 data to inhibit programming of the first number of memory cells while the second number of memory cells is programmed (i.e. applying Vcc to unselect bit lines of unselected erased memory cells, also see support from Kim, 2:9-12 and 5:39-43).
Regarding independent claim 10, Jung teaches a memory device, comprising:
control logic configured to:
load data to be programmed to levels within a first number of levels (FIGS 6-7: loading data for programming states 202 and 204 of 1st Group 200) that are greater than or equal to a first particular level (FIG. 6: states 202 and 204 are greater than state 201);
program first memory cells to the levels within the first number of levels using a first set of program pulses having programming voltages within a first programming voltage range (FIG. 8: programming states 202 and 204 with voltage range corresponding to 1st Group);
load second memory cells with level 0 data to inhibit programming of the second memory cells to be programmed to levels within a second number of levels that are less than a second particular level while the first memory cells are programmed (i.e. inhibiting programming other states 231-214, which are less than state 202, see 7:35-8:41. Kim provides support that each of the bit lines of unselected group of memory cells is applied with Vcc by loading data “0” in a latch of the corresponding page buffer, see 2:9-12 and 5:39-43), wherein the second particular level is greater than the first particular level (FIG. 6: state 202 is greater than state 201);
load data to be programmed to the levels within the second number of levels (FIGS 6-7: loading data for programming states 212 and 214 of 2nd Group 210); and
program the second memory cells to the levels within the second number of levels using a second set of program pulses having programming voltages within a second programming voltage range (FIG. 8: programing states 212 and 214 with voltage range corresponding to 2nd Group), wherein a start programming voltage of the first programming voltage range is substantially equal to a stop programming voltage of the second programming voltage range (see annotated FIG. 8 above).
Regarding dependent claim 14, see rejection applied to claim 10 above.
Regarding independent claim 17, Lee teaches a method of programming a memory, comprising:
loading data for cells to be programmed (FIGS 6-7: loading data for programming states 202 and 204 of 1st Group 200) to a level greater than or equal to a first particular level (FIG. 6: states 202 and 204 are greater than state 201);
loading data for cells to be programmed to a level less than a second particular level with level 0 data (i.e. inhibiting programming other states 231-214, which are less than state 202, see 7:35-8:41. Kim provides support that each of the bit lines of unselected group of memory cells is applied with Vcc by loading data “0” in a latch of the corresponding page buffer, see 2:9-12 and 5:39-43), wherein the second particular level is greater than the first particular level (FIG. 6: state 202 is greater than state 201);
programming the cells to be programmed with program pulses in a first voltage range (FIG. 8: programming states 202 and 204 with voltage range corresponding to 1st Group);
re-loading data for cells to be programmed to a level less than the first particular level with actual data to be programmed (FIGS 6-7: loading data for programming states 212 and 214 of 2nd Group 210); and
programming the re-loaded cells to be programmed with program pulses in a second voltage range (FIG. 8: programing states 212 and 214 with voltage range corresponding to 2nd Group), wherein a start programming voltage of the first programming voltage range is substantially equal to a stop programming voltage of the second, different programming voltage range (see annotated FIG. 8 above).
Regarding dependent claim 20, Lee teaches re-loading data for cells to be programmed to a level greater than or equal to the second particular level with the inhibit level prior to programming the re-loaded cells the program pulses in the second voltage range (because when programing of states 202 and 204 is completed, states 202 and 204 become unselected group and are applied with program inhibit voltage Vcc).
Claims 6, 8, 11-13, 15-16, 19 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lee in view of US 7,602,650 to Jung et al. (hereafter Jung) with support from Kim.
Lee teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claims 6, Jung suggests 16-level memory cells are grouped into first and second programming voltage ranges, each includes different numbers of target threshold voltage states (see 12:47-52). Jung is silent regarding particular voltage values.
Since Lee and Jung are both from the same field of endeavor, the purpose disclosed by Jung would have been recognized in the pertinent art of Lee.
It would have been obvious to one with ordinary skill in the art to realize that the recited particular values are merely design choice depending at least on type of flash memory cells and grouping of states.
Regarding dependent claim 8, Jung teaches the memory comprises a 16 level memory (see FIG. 6). Jung does not explicitly teach the first number of cells are programmed to levels 8-15 and the second number of cells are programmed to levels 0-7. However, Jung suggests the groups may be selected to include different numbers of target threshold voltage states (see 12:47-52).
Regarding dependent claims 11-13, see rejection applied to claim 8 above.
Regarding dependent claims 15-16, see rejection applied to claim 6 above.
Regarding dependent claim 19, see rejection applied to claim 8 above, wherein first particular level and second particular level are the same level.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 6, 8-17, 19-20 have been considered but are moot because of the new ground of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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April 9, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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