CTNF 18/442,547 CTNF 82484 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Group I in the reply filed on 5/27/26 is acknowledged. 08-06 AIA Claim s 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/27/26 . Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 3 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Examiner is unclear as to which figure/embodiment matches the claim language of claim 3 and 6 and therefore cannot interpret what the intended structural meaning of the claims. Additionally, Claim recites the limitation "the second horizontal direction" in line 3. There is insufficient antecedent basis for this limitation in claim 1 or 2. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Yu et al.(US PGPub 2017/0358593) . Claim 1: Yu teaches (Fig. 8A-9B) a three-dimensional memory device, comprising: alternating stacks of insulating layers (232) and electrically conductive layers (246), wherein the alternating stacks are laterally spaced apart from each other by backside isolation assemblies that generally laterally extend along a first horizontal direction (hd1) [0049, 0097, 0104, 0117] (Fig. 8A-B) through entire heights of the alternating stacks; and memory stack structures (55) that vertically extend through a respective one of the alternating stacks, and wherein each of the memory stack structures comprises a respective vertical semiconductor channel (60) and a respective vertical stack of memory elements (50) [0087], wherein: each of the backside isolation assemblies comprises a laterally alternating sequence of backside dielectric isolation walls (72) and backside support pillar structures (155). Backside support pillars vertically extend through the entire height of the alternating stack. The claim does not require both the backside dielectric isolation wall and backside support pillar structures to extend vertically through the entire height of the alternating stack. Claim 2: Yu teaches (Fig. 9B) the backside dielectric isolation walls comprise first-type backside dielectric isolation walls (72); the dielectric support pillar structures comprise first-type dielectric support pillar structures (155); the backside isolation assemblies comprise first backside isolation assemblies; and each of the first backside isolation assemblies comprises a respective laterally alternating sequence of the first-type backside dielectric isolation walls and the first-type dielectric support pillar structures . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3-5, 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable Yu et al.(US PGPub 2017/0358593), as applied to claim 2 above, and further in view of Ochii et al. (US PGPub 2022/0293621) Regarding claim 3, as described above, Yu substantially reads on the invention as claimed, except Yu does not teach each of the first backside isolation assemblies (92), a first subset of the first-type backside dielectric isolation walls (921) is laterally offset along the second horizontal direction relative to a laterally extending segment of one of the first-type backside dielectric isolation walls within a second subset of the first-type backside dielectric isolation walls (922); and the laterally extending segment laterally extends along the first horizontal direction. Ochii teaches (Fig. 14) the first backside isolation assemblies, a first subset of the first-type backside dielectric isolation walls is laterally offset along the second horizontal direction relative to a laterally extending segment of one of the first-type backside dielectric isolation walls within a second subset of the first-type backside dielectric isolation walls; and the laterally extending segment laterally extends along the first horizontal direction [0111-0115] to help reduce device size. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the dielectric isolation walls of Yu to have the offset claimed to help reduce device size as taught by Ochii [0111-0115]. Claim 4: Ochii teaches (Fig. 12,14) the backside isolation assemblies further comprise second backside isolation assemblies; and each of the second backside isolation assemblies comprises a respective laterally alternating sequence of second-type backside dielectric isolation walls and second-type dielectric support pillar structures in which all of the second-type backside dielectric isolation walls are aligned along the first horizontal direction such that geometrical centers of the second-type backside dielectric isolation walls are located within a vertical plane that is perpendicular to the second horizontal direction. Claim 5: Ochii teaches (Fig. 12,14) the first backside isolation assemblies and the second backside isolation assemblies alternate along the second horizontal direction. Claim 7: Ochii teaches (Fig. 12,14) first subset of the memory stack structures is located within a first memory array region in a plan view; a second subset of the memory stack structures is located within a second memory array region in the plan view; the first subset of the second-type backside dielectric isolation walls is located entirely in an inter-array region that is located between the first memory array region and the second memory array region in the plan view; and the second subset of the first-type backside dielectric isolation walls laterally extends along the first horizontal direction within each of the first memory array region and the second memory array region, and comprises at least one tilted portion that is located within the inter- array region and laterally extends along a horizontal direction that is different from the first horizontal direction with a non-zero tilt angle with respect to the first horizontal direction. Claim 15: Ochii teaches (Fig. 12,14) one or more of the first-type dielectric support pillar structures (50D) within the first backside isolation assemblies comprise at least one first lateral indentation that is filled with a respective one of the first-type backside dielectric isolation walls; and one or more of the second-type dielectric support pillar structures within the second backside isolation assemblies comprise at least one second lateral indentation that is filled with a respective one of the second-type backside dielectric isolation walls. Claims 8-10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable Yu et al.(US PGPub 2017/0358593) and Ochii et al. (US PGPub 2022/0293621), as applied to claim 4 above, and further in view of Tobioka (US PGPub 2020/0295040). Regarding claim 8, as described above, Yu and Ochii substantially read on the invention as claimed, except Yu and Ochii do not teach a first retro-stepped dielectric material portion embedded in a first alternating stack of the alternating stacks and contacts one of the second backside isolation assemblies; and a second retro-stepped dielectric material portion embedded in a second alternating stack of the alternating stacks and contacts said one of the second backside isolation assemblies and comprises a same dielectric material as the first retro-stepped dielectric material portion. Tobioka teaches (Fig. 11A) a first retro-stepped dielectric material portion (165) embedded in a first alternating stack of the alternating stacks and contacts one of the second backside isolation assemblies (20); and a second retro-stepped dielectric material portion (265) embedded in a second alternating stack of the alternating stacks and contacts said one of the second backside isolation assemblies (20) and comprises a same dielectric material as the first retro-stepped dielectric material portion as support pillars are needed in the contact region (200) and the memory array region (100) (Fig. 11A).Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the device taught by Yu and Ochii to have had the retro stepped dielectrics in contact with the second backside isolation assemblies because the devices need the support throughout the entirety of the devices including the staircase and memory array regions. Claim 9: Tobioka teaches (Fig. 11A) the first retro-stepped dielectric material portion comprises a first lengthwise sidewall having a first top edge that laterally extends along the first horizontal direction and is laterally spaced from the second-type backside dielectric isolation walls within said one of the second backside isolation assemblies by a first lateral spacing; and the second retro-stepped dielectric material portion comprises a second lengthwise sidewall having a second top edge that laterally extends along the first horizontal direction and is laterally spaced from the second-type backside dielectric isolation walls within said one of the second backside isolation assemblies by a second lateral spacing that is different from the first lateral spacing. Claim 10: Tobioka teaches (Fig. 11A) the first lengthwise sidewall comprises a first stepped bottom edge; the second lengthwise sidewall comprises a second stepped bottom edge; and each of the first lengthwise sidewall and the second lengthwise sidewall includes a respective plurality of horizontally-extending line segments that laterally extend along the first horizontal direction and are interconnected among one another by a respective plurality of vertically-extending line segments. Claim 13: Tobioka teaches (Fig. 11A) first layer contact via structures vertically extending through the first retro-stepped dielectric material portion and contacting a respective electrically conductive layer within the first alternating stack; and second layer contact via structures vertically extending through the second retro-stepped dielectric material portion and contacting a respective electrically conductive layer within the second alternating stack. Claim 14: Yu teaches the first retro-stepped dielectric material portion is not in direct contact with any of the second backside isolation assemblies; and the second retro-stepped dielectric material portion is not in direct contact with any of the second backside isolation assemblies. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SARAH K SALERNO/ Primary Examiner, Art Unit 2814 Application/Control Number: 18/442,547 Page 2 Art Unit: 2814 Application/Control Number: 18/442,547 Page 3 Art Unit: 2814 Application/Control Number: 18/442,547 Page 4 Art Unit: 2814 Application/Control Number: 18/442,547 Page 5 Art Unit: 2814 Application/Control Number: 18/442,547 Page 6 Art Unit: 2814 Application/Control Number: 18/442,547 Page 7 Art Unit: 2814 Application/Control Number: 18/442,547 Page 8 Art Unit: 2814 Application/Control Number: 18/442,547 Page 9 Art Unit: 2814 Application/Control Number: 18/442,547 Page 10 Art Unit: 2814
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