Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 08/19/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered.
Claims 1-20 are currently pending in the present application, with claims 1, 13, and 20 being written in independent form. Claims 1, 4, 7, 13, and 20 have been amended. Claims 8 and 19 have been withdrawn from consideration.
Response to Amendment
Applicant’s amendments to the title have overcome the objection to the Specification.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7, 9-18 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The claim amendment (“side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards”) necessitated new search and More et al. (US 20220052203 A1; hereinafter “More”) has been applied in the current rejection to teach the amended claim limitation, as describe below in the 103 section.
Therefore, claims 1-7, 9-18 and 20 stand rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11-13, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miura et al. (US 20200312658 A1; hereinafter “Miura”) in view of More et al. (US 20220052203 A1; hereinafter “More”).
In re claim 1, Miura discloses in figs. 13-18, a semiconductor device comprising:
a substrate 701 (¶104);
a fin-type active region 702 protruding on the substrate 701;
a channel region on the fin-type active region and comprising a plurality of active patterns 704 extending in a first horizontal direction (e.g., in and out of the paper direction in fig. 13J; hereinafter “Y”) and a semiconductor material layer 715 (¶114);
a gate line 719 (¶117) extending in a second horizontal direction (e.g., east-west direction in fig. 13J; hereinafter “X”), the second horizontal direction X being perpendicular to the first horizontal direction X, and the gate line 719 covering the channel region 704, 715 on the fin-type active region; and
a pair of source/drain regions 710, 710 (¶107) at both sides of the gate line 719 on the fin-type active region702, a work function of the semiconductor material layer 715 being different from a work function of the plurality of active patterns 704 (active patterns 704 formed of SiGe and the semiconductor material layer 715 formed of Silicon; ¶104, 114. Therefore, a work function of the semiconductor material layer 715 is different from a work function of the plurality of active patterns 704),
the semiconductor material layer 715 surrounding portions of the gate line 719 between the plurality of active patterns 704, and
the gate line 719 being separated from the pair of source/drain regions 710, 710 with the semiconductor material layer 715 therebetween.
Miura does not expressly disclose side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards.
In the same field of endeavor, More discloses, in figs. 1-9, a semiconductor device, wherein side surfaces of the plurality of active patterns 122t facing the source/drain regions 602/806 being curved outwards (¶32, 44). Furthermore, More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards in the device of Miura as More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32 of More).
In re claim 11, Miura in view of More discloses the semiconductor device of claim 1 outlined above.
Miura further discloses in figs. 13-18, wherein a material constituting the plurality of active patterns 704 includes silicon germanium (¶104), and a material constituting the semiconductor material layer 715 includes silicon (¶114).
Miura does not expressly disclose wherein a material constituting the plurality of active patterns includes silicon, and a material constituting the semiconductor material layer includes silicon germanium.
In the same field of endeavor, More discloses, in figs. 1-9, the semiconductor device, wherein a material constituting the plurality of active patterns 122 includes silicon, and a material constituting the semiconductor material layer 124 includes silicon germanium (¶24; “In some embodiments, each of semiconductor layers 122 can be formed of silicon and each of semiconductor layers 124 can be formed of silicon germanium (SiGe). In some embodiments”.).
Based on More’s teachings, Miura’s core and peripheral channel regions materials can be alternately formed by Si and SiGe.
One of ordinary skill in the art could have substituted Miura’s core and peripheral channel regions materials based on More’s express suggestion to substitute with Si and SiGe such that two layers have selectivity different from each other (¶24 of More).
MPEP § 2143(I)(B) states “Simple Substitution of One Known Element for Another To Obtain Predictable Results” is prima facie case of obviousness.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to combine the teachings of Miura and More to
arrive at the claimed invention.
In re claim 12, Miura, as modified by More, discloses the semiconductor device of claim 11 outlined above.
More further discloses wherein a germanium concentration of the silicon germanium in the semiconductor material layer 124 is 20 % to 60 % (¶38 or More, “For example, semiconductor layers 124 can have a germanium atomic content ratio of about 25%”).
In re claim 13, Miura discloses, in figs. 13-18, a semiconductor device comprising:
a substrate 701 including a first area pMOS and a second area nMOS (¶104-105);
first and second fin-type active regions 702, 703, 704 protruding on the substrate 701 (¶104-105);
a first channel region 704 on the first fin-type active region and comprising a plurality of first active patterns 704 extending in a first horizontal direction (e.g., in and out of the paper direction in fig. 13J; hereinafter “Y”) and a semiconductor material layer 715 surrounding at least portions of the plurality of first active patterns 704 (fig. 17; ¶114);
a first gate line 716, 718, 719 (¶117) covering the first channel region on the first fin-type active region 704;
a second channel region 703 on the second fin-type active region and comprising a plurality of second active patterns 703 extending in the first horizontal direction Y,
a second gate line 716, 717, 719 (¶117) covering the second channel region 703 on the second fin-type active region;
a pair of first source/drain regions 710, 710 (¶107) at both sides of the first gate line 719 on the first fin-type active region 704; and
a pair of second source/drain regions 713, 713 (¶107-108) at both sides of the second gate line 719 on the second fin-type active region,
the first fin-type active region 704 being in the first area of the substrate pMOS,
the second fin-type active region 703 being in the second area of the substrate nMOS, and
in the semiconductor material layer 715, at least one of a surface in contact with the plurality of first active patterns 704,
a surface in contact with the first gate line 716, 717, 719 being a curved surface (see fig. 13J; the limitation “curved” has been interpreted as a non-linear surface, as no degree of curvature has been claimed to distinguish over Miura’s square shaped surfaces).
Miura does not expressly disclose side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards.
In the same field of endeavor, More discloses, in figs. 1-9, a semiconductor device, wherein side surfaces of the plurality of active patterns 122t facing the source/drain regions 602/806 being curved outwards (¶32, 44). Furthermore, More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards in the device of Miura as More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32 of More).
In re claim 16, Miura in view of More discloses the semiconductor device of claim 13 outlined above.
Miura discloses, in figs. 13-18, the semiconductor device of claim 13, further comprising:
a first device isolation layer (705 in the pMOS area) covering both side surfaces of the first fin-type active region 702, 704 (¶104); and
a second device isolation layer (705 in the nMOS area) covering both side surfaces of the second fin-type active region 702, 703 (¶104),
wherein a thickness of the first device isolation layer 705 is less than or equal to a thickness of the second device isolation layer 705 (a thickness of the first device isolation layer 705 is equal to a thickness of the second device isolation layer 705).
Claim(s) 2-3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miura in view of More, as applied to claim 1 above, and further in view of Lin et al. (US 20240312997 A1; hereinafter “Lin”).
In re claim 2, Miura in view of More discloses the semiconductor device of claim 1 outlined above.
Miura in view of More does not expressly disclose the semiconductor device further comprising a pair of inner spacers separated from each other in the first horizontal direction, wherein a portion of the gate line between two adjacent active patterns is at one side of each of the pair of inner spacers and the semiconductor material layer is at the other side thereof.
In the same field of endeavor, Lin discloses in figs. 1-2, a semiconductor device comprising a pair of inner spacers 132 (¶50) separated from each other in a first horizontal direction X, wherein a portion of a gate line 150 (¶27) between two adjacent active patterns 116 is at one side of each of the pair of inner spacers 132 and a semiconductor material layer 134 (¶52-53) is at the other side thereof.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lin and form inner spacers in the semiconductor device of Miura in view of More to utilize spacers to pattern the GAA structure and to improve the parasitic capacitance, thereby enhancing the performance of the device (¶22, 52 of Lin).
In re claim 3, Miura, as modified by More and Lin, discloses semiconductor device of claim 2, wherein both sidewalls of each of the pair of inner spacers (Lin: fig. 2C; element 132) have curved surfaces recessed inward.
In re claim 9, Miura in view of More discloses the semiconductor device of claim 1, wherein one side of each of both sidewalls of the semiconductor material layer 715 is in contact with each of the pair of source/drain regions 710, 710 (see fig. 16E).
Miura in view of More does not expressly disclose both the sidewalls of the semiconductor material layer have a shape in which centers of both the sidewalls of the semiconductor material layer recess toward the gate line.
In the same field of endeavor, Lin discloses in figs. 1-2, a semiconductor device comprising both the sidewalls of the semiconductor material layer 134 have a shape in which centers of both the sidewalls of the semiconductor material layer 134 recess toward the gate line 150 (¶27, 52-53).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lin and form the semiconductor material layer having a shape in which centers of both the sidewalls of the semiconductor material layer recess toward the gate line in the semiconductor device of Miura in view of More.
It would have been obvious to one of ordinary skill in the art to modify the shape of the semiconductor layer and the gate line of Miura in view of More and employ the shape taught by Lin and to arrive at the claimed invention since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miura in view of More and Lin, as applied to claim 2 above, and further in view of Cheng et al. (US 20190035913 A1; hereinafter “Cheng”).
In re claim 4, Miura, as modified by More and Lin, discloses the semiconductor device of claim 2 outlined above, but does not expressly disclose wherein both sidewalls of the portion of the gate line between two adjacent active patterns are curved surfaces protruding outward.
In the same field of endeavor, Cheng discloses a semiconductor device in figs. 3-16, wherein both sidewalls of a portion of a gate line 332 between two adjacent active patterns 312 are curved surfaces protruding outward (¶88-90).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Cheng into the device of Miura, as modified by More and Lin, to trim the nanosheet layers to the desired channel thickness, thereby producing faceted surfaces between the subset of the set of nanosheet layers and the inner spacer (¶11, 85).
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miura in view of More, as applied to claim 1 above, and further in view of Mochizuki et al. (US 20230065852 A1; hereinafter “Mochizuki”).
In re claim 6, Miura in view of More discloses the semiconductor device of claim 1 outlined above, but does not expressly disclose the semiconductor device of claim 1, wherein upper and lower surfaces of each of the plurality of active patterns are curved surfaces recessed inward.
In the same field of endeavor, Mochizuki discloses in figs. 16A-16B, a semiconductor device, wherein upper and lower surfaces of each of the plurality of active patterns 108a-108c are curved surfaces recessed inward (¶51-52).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Mochizuki and form upper and lower surfaces of each of the plurality of active patterns as curved surfaces recessed inward in the semiconductor device of Miura in view of More to incorporate a circuit design which attains a strained channel MOSFET device with higher performance (¶2-6 of Mochizuki).
In re claim 7, Miura, as modified by More and Mochizuki, discloses the semiconductor device of claim 6 outlined above.
Miura further discloses in figs. 13-18, the semiconductor device of claim 6, wherein, in a region in which the semiconductor material layer 715 is in contact with the plurality of active patterns 704, the semiconductor material layer 715 is conformally formed along the surfaces of the plurality of active patterns 704 (see fig. 17).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miura in view of More, as applied to claim 1 above.
In re claim 10, Miura in view of More discloses the semiconductor device of claim 1 outlined above.
Miura further discloses in figs. 13-18, wherein the thickness of the silicon segregation layer 715 formed at the second step is less than 1 nm (¶68), which is merely close to the claimed range of 1 nm to 1.5 nm.
MPEP §2144.05-I states a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of "having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium" as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium. "The proportions are so close that prima facie one skilled in the art would have expected them to have the same properties."). In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%).
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Miura to form the semiconductor layer having a thickness between 1 nm and 1.5 nm to protect SiGe channel without damaging the SiGe channel (¶16 of Miura).
Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki et al. (US 20230065852 A1; hereinafter “Mochizuki”) in view of More et al. (US 20220052203 A1; hereinafter “More”).
In re claim 13, Mochizuki discloses in figs. 1-16B, a semiconductor device comprising:
a substrate 104 including a first area 102a and a second area 102b (¶51);
first and second fin-type active regions (108a-108c in the first and second areas 102a, 102b) protruding on the substrate 104 (¶51-52);
a first channel region (region of the fins 108a-108c underneath the gate in area 102a; hereinafter “CH1”) on the first fin-type active region and comprising a plurality of first active patterns108a-108c extending in a first horizontal direction (e.g., in and out of the paper direction; hereinafter “Y”) and
a semiconductor material layer 130 surrounding at least portions of the plurality of first active patterns 108a-108c (fig. 16; ¶72);
a first gate line 134, 136, 138 covering the first channel region on the first fin-type active region (region of the fins 108a-108c underneath the gate in area 102a) (¶75-76);
a second channel region (region of the fins 108a-108c underneath the gate in area 102b; hereinafter “CH2”) on the second fin-type active region and comprising a plurality of second active patterns 108a-108c extending in the first horizontal direction Y,
a second gate line 134, 136, 138 covering the second channel region (CH2) on the second fin-type active region;
a pair of first source/drain regions 122a, 122a (¶65) at both sides of the first gate line 134, 136, 138 on the first fin-type active region 108a-108c; and
a pair of second source/drain regions 122b, 122b (¶65) at both sides of the second gate line 134, 136, 138 on the second fin-type active region 108a-108c,
the first fin-type active region 108a-108c being in the first area of the substrate 102a,
the second fin-type active region 108a-108c being in the second area of the substrate 102b, and
in the semiconductor material layer 130, at least one of a surface in contact with the plurality of first active patterns 108a-108c,
a surface in contact with the first gate line 134, 136, 138 being a curved surface (figs. 16A-16B).
Mochizuki does not expressly disclose side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards.
In the same field of endeavor, More discloses, in figs. 1-9, a semiconductor device, wherein side surfaces of the plurality of active patterns 122t facing the source/drain regions 602/806 being curved outwards (¶32, 44). Furthermore, More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards in the device of Mochizuki as More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32 of More).
In re claim 14, Mochizuki in view of More discloses the semiconductor device of claim 13 outlined above.
Mochizuki discloses in figs. 1-16B, the semiconductor device of claim 13, wherein a thickness of each of the plurality of first active patterns 108a-108c in the first channel region CH1 is less than a thickness of each of the plurality of second active patterns 108a-108c in the second channel region CH2.
In re claim 15, Mochizuki in view of More discloses the semiconductor device of claim 13 outlined above.
Mochizuki discloses in figs. 1-16B, the semiconductor device of claim 13, wherein a sum of a thickness of each of the plurality of first active patterns 108a-108c in the first channel region CH1 and a thickness of the semiconductor material layer 130 is same as a thickness of each of the plurality of second active patterns 108a-108c in the second channel region CH2.
In re claim 16, Mochizuki in view of More discloses the semiconductor device of claim 13 outlined above.
Mochizuki discloses, in figs. 1-16B, the semiconductor device of claim 13, further comprising:
a first device isolation layer 112 covering both side surfaces of the first fin-type active region 108a-108c (¶57); and
a second device isolation layer 112 covering both side surfaces of the second fin-type active region 108a-108c,
wherein a thickness of the first device isolation layer 112 is less than or equal to a thickness of the second device isolation layer 112 (a thickness of the first device isolation layer 112 is equal to a thickness of the second device isolation layer 112).
In re claim 17, Mochizuki in view of More discloses the semiconductor device of claim 13 outlined above.
Mochizuki discloses, in figs. 1-16B, the semiconductor device of claim 13, further comprising
a pair of first inner spacers 120, 120 and a pair of second inner spacers 120, 120 (¶63-65),
wherein the pair of first inner spacers 120, 120 are at both sides of a portion of the first gate line 134, 136, 138 between two adjacent first active patterns 108a-108c (in area 102a),
both the sides of the portion of the first gate line 134, 136, 138 facing each other in the first horizontal direction Y,
the pair of second inner spacers 120, 120 are at both sides of a portion of the second gate line 134, 136, 138 between two adjacent second active patterns 108a-108c (in area 102b),
both the sides of the portion of the second gate line 134, 136, 138 facing each other in the first horizontal direction Y,
each of the pair of first inner spacers 120, 120 is in contact with an adjacent one of the pair of first source/drain regions 122a, 122a, and
each of the pair of second inner spacers 120, 120 is in contact with an adjacent one of the pair of second source/drain regions 122b, 122b.
In re claim 18, Mochizuki discloses in figs. 1-16B, the semiconductor device of claim 16,
wherein both sidewalls of a portion of the first gate line 134, 136, 138 between two adjacent first active patterns 108a-108c,
both the sidewalls of the portion of the first gate line 134, 136, 138 facing each other in the first horizontal direction Y, and
both sidewalls of a portion of the second gate line 134, 136, 138 between two adjacent second active patterns 108a-108c,
both the sidewalls of the portion of the second gate line 134, 136, 138 facing each other in the first horizontal direction Y.
Mochizuki does not expressly disclose both the sidewalls of the portion of the first gate line and both the sidewalls of the portion of the second gate line have curved surfaces recessed inward.
In the same field of endeavor, More discloses, in figs. 1-12, a semiconductor device, wherein both sidewalls of a portion of a gate line 1116/1114/1112 have curved surfaces recessed inward (fig. 11; ¶51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of More with Mochizuki and form both the sidewalls the first and second gate lines as having curved surfaces recessed inward as More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 (which is turn results in gate lines having curved surfaces recessed inward) and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32 of More).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mochizuki in view of Lin et al. (US 20240312997 A1; hereinafter “Lin”) and More et al. (US 20220052203 A1; hereinafter “More”).
In re claim 20, Mochizuki discloses in figs. 1-16B, a semiconductor device comprising:
a substrate 104 including a first area 102a and a second area 102b (¶51);
first and second fin-type active regions (108a-108c in the first and second areas 102a, 102b) protruding on the substrate 104 (¶51-52);
a first channel region (region of the fins 108a-108c underneath the gate in area 102a; hereinafter “CH1”) on the first fin-type active region and comprising a plurality of first active patterns 108a-108c extending in a first horizontal direction (e.g., in and out of the paper direction; hereinafter “Y”) and
a semiconductor material layer 130 surrounding at least portions of the plurality of first active patterns 108a-108c (fig. 16; ¶72);
a first gate line 134, 136, 138 covering the first channel region on the first fin-type active region (region of the fins 108a-108c underneath the gate in area 102a) (¶75-76);
a pair of first inner spacers 120 separated from each other in the first horizontal direction Y with the first gate line 134, 136, 138 therebetween (¶63-64);
a second channel region (region of the fins 108a-108c underneath the gate in area 102b; hereinafter “CH2”) on the second fin-type active region and comprising a plurality of second active patterns 108a-108c extending in the first horizontal direction Y,
a second gate line 134, 136, 138 covering the second channel region (CH2) on the second fin-type active region;
a pair of first source/drain regions 122a, 122a (¶65) at both sides of the first gate line 134, 136, 138 on the first fin-type active region 108a-108c; and
a pair of second source/drain regions 122b, 122b (¶65) at both sides of the second gate line 134, 136, 138 on the second fin-type active region 108a-108c,
the first fin-type active region 108a-108c being in the first area of the substrate 102a,
the second fin-type active region 108a-108c being in the second area of the substrate 102b,
a work function of the semiconductor material layer 130 (e.g., SiGe layer; ¶72) being different from a work function of the plurality of first active patterns 108a-108c (e.g., Si layer; ¶64),
the semiconductor material layer 130 surrounding a portion of the first gate line 134, 136, 138 between two adjacent first active patterns 108a-108c.
Mochizuki does not expressly disclose the semiconductor material layer 130 surrounding the pair of first inner spacers, and
the first gate line being separated from the pair of first source/drain regions with the semiconductor material layer and the pair of first inner spacers therebetween.
In the same field of endeavor, Lin discloses in figs. 1-2 ((¶50-53), a semiconductor device comprising:
a pair of inner spacers 132 separated from each other in a first horizontal direction X,
the semiconductor material layer 134 surrounding the pair of first inner spacers 132, and
the first gate line 150 being separated from the pair of first source/drain regions 140, 140 with the semiconductor material layer 134 and the pair of first inner spacers 132 therebetween.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Lin and form inner spacers in the semiconductor device of Mochizuki to utilize spacers to pattern the GAA structure and to improve the parasitic capacitance, thereby enhancing the performance of the device (¶22, 52 of Lin).
Mochizuki in view of Lin does not expressly disclose side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards.
In the same field of endeavor, More discloses, in figs. 1-9, a semiconductor device, wherein side surfaces of the plurality of active patterns 122t facing the source/drain regions 602/806 being curved outwards (¶32, 44). Furthermore, More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the side surfaces of the plurality of active patterns facing the source/drain regions being curved outwards in the device of Mochizuki in view of Lin as More discloses the non-planar (e.g., curved) outer surfaces of inner spacers 127 and semiconductor layers 122 can reduce voids in subsequently formed source/drain structures by removing sharp corners where voids tend to form (¶32 of More).
Allowable Subject Matter
Claim(s) 5 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, closest prior art of record, alone or in combination, does not expressly disclose the device comprising a semiconductor cap surrounding the gate line and the pair of inner spacers, in combination with all other limitations cited in claims 1 and 2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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