Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 13
b. Pending: 1-21
Claim 11 have been amended and claim 21 have been added.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Behrends et al. (US 20120147661) in view of Furutani et al. (US 6551846).
Regarding independent claim 1, Behrends discloses a semiconductor device (Figs. 1-6) comprising:
a power control signal generation circuit configured to generate a power control signal that is activated when at least one of a power-up period is started (Figs. 1-2 and [0019] describes that POR- signal 128 is preferably generated on the DRAM chip to increase security. Methods and circuits for generating a POR- signal in response to energization of an integrated circuit by a power supply are known in the prior art. Fig. 6 at step 610 states “generate a power on reset (POR)) and a test mode operation is performed; and
an operating power generation circuit configured to set operating power supplied to a word line driver as a high voltage responsive to the power control signal (Fig. 6 and [0024] describes use the POR signal to drive the wordlines of all the memory cells in the memory cell array (step 620)).
Behrends doesn’t explicitly disclose test mode operation; and word line driver as a high voltage;
However, Furutani teaches test mode operation; and word line driver as a high voltage (Fig. 23 and (128) describes when test mode instruction signal ZTE is activated, to transmit external supply voltage Vex as boosted voltage. High voltage Vpp is supplied to the row selection circuit and the H level of a selected word line (sub word line) is set at high voltage Vpp level);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Furutani to Behrends in order to provide mechanism that in response to activation of test mode word line latch instruction signal TM_WLLTC, WL reset circuit 502 maintains word line reset timing signal WLOFF in the inactive state. A timing signal from level shifter 503 thus maintains H level and selected word line WL1 maintains the selected state as taught by Furutani ((20)).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Behrends et al. (US 20120147661) in view of Furutani et al. (US 6551846) and Lee (US 20130113532).
Regarding claim 2, Behrends and Furutani together disclose all the elements of claim 1 as above and through Lee further the power control signal generation circuit is configured to generate the power control signal by receiving a power-up signal during a power-up period (Fig. 1 and [0019] describes that power control unit 102 receives the reset signal Sreset and generates a power enabling signal Spe according to the reset signal Sreset to the power supply unit 100).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Behrends in order to provide with power control unit that receives the reset signal and generates a power enabling signal according to the reset signal as taught by Lee ([0006]).
Regarding claim 12, Behrends and Furutani together disclose all the elements of claim 1 as above and through Lee further the operating power generation circuit is configured to maintain a voltage level of the operating power so that the voltage level of the operating power does not drop below a predetermined a voltage level when the power control signal is deactivated (Fig. 3 and [0027] describes that the power supply unit 100 outputs the standby voltage Vsb to the reset unit 101, value of the standby Vsb is higher than a threshold value (i.e. approximately equal 2.93V) which is predetermined by the controller 31).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Behrends in order to provide with power control unit that receives the reset signal and generates a power enabling signal according to the reset signal as taught by Lee ([0006]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Behrends et al. (US 20120147661) in view of Furutani et al. (US 6551846) and Kim et al. (US 9202556).
Regarding claim 3, Behrends and Furutani together disclose all the elements of claim 1 as above and through Kim further the power control signal generation circuit is configured to generate the power control signal, by receiving a test mode signal when the test mode operation is performed (Fig. 2 and (35) describes test mode signal TM2 and the second enablement signal EN2 to generate the power control signal PWRGT)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kim to modified Behrends in order to provide with power control signal generator that generates a power control signal PWRGT enabled from a point of time that a power-up signal PWR is enabled till a point of time that a mode set signal MRSP is enabled and is enabled in response to first and second test mode signals TM<1:2> as taught by Kim ((11)).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Behrends et al. (US 20120147661) in view of Furutani et al. (US 6551846) and Tanaka et al. (US 20160300912).
Regarding claim 10, Behrends and Furutani together disclose all the elements of claim 1 as above and through Tanaka further the operating power generation circuit comprises a switching element that is connected between an output voltage node and the high voltage and which is configured to be turned on and off responsive to the power control signal (Fig. 31 and [0161]-[0162] describes switch S1 connected between an output voltage node 61 and the high voltage node HV. The connection point 61 is an output point of the power conversion unit 60).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanaka to modified Behrends in order to provide with technology such that an increase in the resistance of a resistive element can be achieved while restricting an increase in size of a semiconductor device as taught by Tanaka ([0012]).
Regarding claim 11, Behrends, Furutani and Tanaka together disclose all the elements of claim 10 as above and through Tanaka further the operating power generation circuit additionally comprises at least one diode element that is connected in parallel to the switching element between an output voltage node and the high voltage (Fig. 31 and [0161]-[0162] shows diode FWD1 connected in parallel to switch S1).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tanaka to modified Behrends in order to provide with technology such that an increase in the resistance of a resistive element can be achieved while restricting an increase in size of a semiconductor device as taught by Tanaka ([0012]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Behrends et al. (US 20120147661) in view of Furutani et al. (US 6551846) and Lee et al. (US 20190164596).
Regarding claim 21, Behrends and Furutani together disclose all the elements of claim 1 as above and through Lee further the word line driver receives row addresses to drive word lines as the operating power (Fig. 16 and [0128] describes pre-decoder 260 may decode the row address RA to provide a decoded row address DRA to the plurality of word-line drivers 231˜23n. At least one of the plurality of word-line drivers 231˜23n, which receives a bit having a second logic level of bits of the decoded row address DRA, may drive a corresponding word-line with the word-line driving voltage based on the word-line power voltage VDDWL. Here pre-decoder 260 along with rest of the circuitry together forms word line driver).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Behrends in order to provide with a memory device including a memory cell array and a peripheral circuit, a voltage generation circuit in the peripheral circuit adaptively adjusts a word-line driving voltage based on a difference between a first power supply voltage provided to the memory cell array and a second power supply voltage provided to the peripheral circuit during a memory operation. Therefore, the memory device may ensure operation stability while maintaining and/or enhancing operation performance during the memory operation as taught by Lee ([0008]).
Allowable Subject Matter
Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-20 are allowed.
Response to Arguments
Applicant's arguments filed on 1/12/2026 have been fully considered but they are not persuasive.
Pg. 7: Header A. talks about power control signal. Examiner respectfully disagrees.
POR is a power signal that starts during power on process.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., Pg. 8 features) are not recited in the rejected claim. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Pg. 9: Header B. talks about power generation circuit. Examiner respectfully disagrees.
Behrends in Figs. 3-5 and corresponding section of the specification discloses that decode circuit 312 normally drives one of wordlines 412 depending on pre-decode outputs which are determined by the particular address on the address bits 412 based on POR signal.
Furutani in Figs. 22-23 and corresponding section of the specification discloses power supply circuit operating based on test mode.
In response to applicant's argument, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Claim 1 does not recite dual-condition activation, rather it recites one of a two condition scenario.
Pg. 10: Header C. talks about motivation to combine.
Another motivation to combine teachings of Furutani to Behrends on top of the one already mentioned in NFA is to provide a semiconductor memory device capable of driving a plurality of word lines simultaneously into selected state speedily with a small number of signals.
Rejections are maintained for above reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection for new claim 21 presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 3/11/2026