DETAILED ACTION
This Office Action is in response to Restriction/Elected, filed on 12/09/2025, on the application filed on 02/15/2024. Claims 1-10 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant timely traversed the restriction (election) in the reply filed on 12/09/2025. The Response to Restriction/Election of claims 6-10 (mailed 10/20/2025) has been fully considered and are persuasive.
Claims 6-10 that previously was withdrawn from consideration as a result of a restriction requirement, is hereby rejoined and fully examined for patentability under 37 CFR 1.104.
Because claims 6-10 previously withdrawn from consideration under 37 U.S.C. 121 and 372 has been REJOINED, the restriction requirement as set forth in the Office action mailed on 10/20/2025 is hereby withdrawn. In view of the withdrawal of the restriction requirement as to the rejoined inventions, applicant(s) are advised that if any claim presented in a continuation or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In independent claim 1, the limitation phrase “specification” in the limitations “and a specification of the first circuit structure is the same as a specification of the second circuit structure” & “wherein a specification of the wiring structure is different from the specification of the first circuit structure” is confusing. Specifically, though the limitation phrase “specification” is specifically indicated in the abstract and ¶[0009 & 0056] of the PgPub, where ¶[0013] indicates “specification is a line width and/or a line pitch”, the limitation phrase “specification” is an OPEN ENDED PARAMETER limitation in relation to “first circuit structure”, “second circuit structure”, and “wiring structure”. Thus, the limitation phrase “specification” is a RELATIVE TERM that renders the claim INDEFINATE. In addition, IF the cited limitation phrase “specification” is amended to “line width/line pitch”, the specification does not provide a standard (range or value) for ascertaining what would be “line width” (what degree of measurement is the line width?) or/and “line pitch” (what is the distance measured from the center of one conductive trace/line to the center of the adjacent conductive trace defining the routing density of the board?). Therefore, the TERM “parameter” would ALSO render the claim INDEFINATE. Consequently, one of ordinary skill in the art would not be reasonably appraised of the scope of the invention. Therefore, the cited limitation phrase in the cited limitations has been construed to cover ANY “specification” without regard to what applicant may or may not consider being acceptable.
Claims 2-5 are rejected since base independent claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In claim 2, the limitation phrase “specification” in the limitation “such that a specification of the redistribution layer is different from a specification of the first circuit layer, and a specification of the second circuit layer is the same as the specification of the first circuit layer” is confusing. Specifically, though the limitation phrase “specification” is specifically indicated in ¶[0010] of the PgPub, where ¶[0041 & 0045] indicates “specification (e.g., line width/line pitch)”, the limitation phrase “specification” is an OPEN ENDED PARAMETER in relation to “redistribution layer”, “first circuit layer”, and “second circuit layer”. Thus, the limitation phrase “specification” is a RELATIVE TERM that renders the claim INDEFINATE. In addition, IF the cited limitation phrase “specification” is amended to “line width/line pitch”, the specification does not provide a standard (range or value) for ascertaining what would be “line width” (what degree of measurement is the line width?) or/and “line pitch” (what is the distance measured from the center of one conductive trace/line to the center of the adjacent conductive trace defining the routing density of the board?). Therefore, the TERM “parameter” would ALSO render the claim INDEFINATE. Consequently, one of ordinary skill in the art would not be reasonably appraised of the scope of the invention. Therefore, the cited limitation phrase in the cited limitations has been construed to cover ANY “specification” without regard to what applicant may or may not consider being acceptable.
In claim 4, the limitation phrase “specification” in the limitation “wherein the specification is a line width and/or a line pitch” is confusing. Specifically, though the limitation phrase “specification” is specifically indicated in ¶[0013] of the PgPub, where ¶[0013] indicates “specification is a line width and/or a line pitch”, the limitation phrase “specification” is an OPEN ENDED PARAMETER limitation. Thus, the limitation phrase “specification” is a RELATIVE TERM that renders the claim INDEFINATE. In addition, IF the cited limitation phrase “specification” is amended to “line width/line pitch”, the specification does not provide a standard (range or value) for ascertaining what would be “line width” (what degree of measurement is the line width?) or/and “line pitch” (what is the distance measured from the center of one conductive trace/line to the center of the adjacent conductive trace defining the routing density of the board?). Therefore, the TERM “parameter” would ALSO render the claim INDEFINATE. Consequently, one of ordinary skill in the art would not be reasonably appraised of the scope of the invention. Therefore, the cited limitation phrase in the cited limitations has been construed to cover ANY “specification” without regard to what applicant may or may not consider being acceptable.
In method independent claim 6, the limitation phrase “specification” in the limitations “wherein a specification of the first circuit layer is the same as a specification of the second circuit layer” & “and a specification of the redistribution layer is different from the specification of the first circuit layer” is confusing. Specifically, though the limitation phrase “specification” is specifically indicated in ¶[0010] of the PgPub, where ¶[0041 & 0045] indicates “specification (e.g., line width/line pitch)”, the limitation phrase “specification” is an OPEN ENDED PARAMETER in relation to “first circuit layer”, “second circuit layer”, and “redistribution layer”. Thus, the limitation phrase “specification” is a RELATIVE TERM that renders the claim INDEFINATE. In addition, IF the cited limitation phrase “specification” is amended to “line width/line pitch”, the specification does not provide a standard (range or value) for ascertaining what would be “line width” (what degree of measurement is the line width?) or/and “line pitch” (what is the distance measured from the center of one conductive trace/line to the center of the adjacent conductive trace defining the routing density of the board?). Therefore, the TERM “parameter” would ALSO render the claim INDEFINATE. Consequently, one of ordinary skill in the art would not be reasonably appraised of the scope of the invention. Therefore, the cited limitation phrase in the cited limitations has been construed to cover ANY “specification” without regard to what applicant may or may not consider being acceptable.
Claims 7-10 are rejected since base independent claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In claim 9, the limitation phrase “specification” in the limitation “wherein the specification is a line width and/or a line pitch” is confusing. Specifically, though the limitation phrase “specification” is specifically indicated in ¶[0013] of the PgPub, where ¶[0013] indicates “specification is a line width and/or a line pitch”, the limitation phrase “specification” is an OPEN ENDED PARAMETER limitation. Thus, the limitation phrase “specification” is a RELATIVE TERM that renders the claim INDEFINATE. In addition, IF the cited limitation phrase “specification” is amended to “line width/line pitch”, the specification does not provide a standard (range or value) for ascertaining what would be “line width” (what degree of measurement is the line width?) or/and “line pitch” (what is the distance measured from the center of one conductive trace/line to the center of the adjacent conductive trace defining the routing density of the board?). Therefore, the TERM “parameter” would ALSO render the claim INDEFINATE. Consequently, one of ordinary skill in the art would not be reasonably appraised of the scope of the invention. Therefore, the cited limitation phrase in the cited limitations has been construed to cover ANY “specification” without regard to what applicant may or may not consider being acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US20230014913A1 and Chen hereinafter).
Regarding claim 1, Chen discloses a package substrate (item 100 of Fig. 7 and ¶[0034] shows and indicates package substrate 100 {wafer 100}), comprising: a core board body having a first side, a second side opposing the first side, and at least one conductive via communicating with the first side and the second side (items 134, 114, 144, 116 of Fig. 7 and ¶[0032-0034_0036 & 0038-0040_0043 & 0051] shows and indicates core board body 134 {encapsulant 134, indicated in ¶[0038-0039 & 0051]} having first side 134_114 {encapsulant 134 side edge adjacent to the under-bump metallurgy layers (UBMLs) 114 side edge, indicated in ¶[0032-0034_0036 & 0038]}, second side 134_144 {encapsulant 134 side edge adjacent to the metallization layers 144 side edge, indicated in ¶[0039-0043]} opposing first side 134_114, and conductive via 116 {indicated in ¶[0033_0038-0040 & 0043]} communicating with first side 134_114 and second side 134_144); a first circuit structure disposed on the first side of the core board body and electrically connected to the conductive via (item 114 of Fig. 7 and ¶[0032-0034_0036 & 0038] shows and indicates first circuit structure 114 {under-bump metallurgy layers (UBMLs) 114} disposed on first side 134_114 of core board body 134 and electrically connected to conductive via 116); a second circuit structure disposed on the second side of the core board body and electrically connected to the conductive via, wherein a number of wiring layers of the second circuit structure is greater than a number of wiring layers of the first circuit structure (item 140, 144, 146 of Fig. 7 and ¶[ 0039-0044] shows and indicates second circuit structure 140 {redistribution structure 140, indicated in ¶[0039 & 0042-0043]} disposed on second side 134_144 of core board body 134 and electrically connected to conductive via 116; where the number of wiring layers 144 & 146 {metallization layers 144, indicated in ¶[0039-0043], and under-bump metallizations (UBMs) 146, indicated in ¶[0043-0044]; where metallization layers 144 and UBMs 146 forms redistribution structure 140} of second circuit structure 140 is greater than the number of wiring layer 114-wiring {wiring forming UBMs 114} of first circuit structure 114), and a specification of the first circuit structure is the same as a specification of the second circuit structure (Fig. 7 and ¶[0032-0034_0036_0038- 0039 & 0042-0043] shows the conical via shape specification of first circuit structure 114 is the same as the conical via shape specification of second circuit structure 140); and a wiring structure disposed on the first circuit structure and electrically connected to the first circuit structure (item 56 of Fig. 7 and ¶[ 0022-0024 & 0030-0032] shows and indicates wiring structure 56 {die connectors 56} disposed on first circuit structure 114 and electrically connected to first circuit structure 114), wherein a specification of the wiring structure is different from the specification of the first circuit structure (Fig. 7 and ¶[ 0022-0024_0030-0034_0036 & 0038] shows where the conductive block shape specification of wiring structure 56 is different from the conical via shape specification of first circuit structure 114); wherein a coefficient of thermal expansion of the second circuit structure is equal to a coefficient of thermal expansion of the first circuit structure with the wiring structure as a whole (Fig. 7 and ¶[0021-0022_0032-0033 & 0043] indicates where the coefficient of thermal expansion of second circuit structure 140 is equal to the coefficient of thermal expansion of first circuit structure 114 with wiring structure 56 as a whole {redistribution structure 140 formed of UBMs 146 and metallization layers 144, where UBMs 146 may be formed of the same copper material as the metallization layers 144, indicated in [0021 & 0043]; die connector 56 can be formed of a metal, such as copper, and a single seed layer of conductive material such as copper forms UBMLs 114, indicated in [0022 & 0032-0033]; therefore, the coefficient of thermal expansion of redistribution structure 140 is equal to the coefficient of thermal expansion of UBMLs 114 & die connector 56}).
Regarding claim 2, Chen discloses a package substrate, wherein the first circuit structure has at least one first insulating layer and a first circuit layer embedded in the first insulating layer, the second circuit structure has at least one second insulating layer and a second circuit layer bonded with the second insulating layer, and the wiring structure has at least one dielectric layer and a redistribution layer bonded with the dielectric layer, such that a specification of the redistribution layer is different from a specification of the first circuit layer, and a specification of the second circuit layer is the same as the specification of the first circuit layer (items 112, 120, 148, 142, 58, 50 of Fig. 7 and ¶[0024_0032_0034_0037_0039-0042 & 0044] shows and indicates where first circuit structure 114 has first insulating layer 112 {dielectric layer 112, indicated in ¶[0032 & 0034]} and first circuit layer 114_120 {circuitry of UBMs 114 connecting to interconnection dies 120, indicated in ¶[0034 & 0037]} embedded in first insulating layer 112; and where second circuit structure 140 has second insulating layer 142 {dielectric layer 142, indicated in ¶[0039-0040]} and second circuit layer 148_146_142 {circuitry between conductive connectors 148, indicated in ¶[0044], and UBMs 146 embedded within second insulating layer 142} bonded with second insulating layer 142; and where wiring structure 56 has dielectric layer 58 {indicated in ¶[0024 & 0030]} and redistribution layer 50 {integrated circuit die 50, indicated in ¶[0024]} bonded with dielectric layer 58 {indicated in ¶[0024 & 0030]} such that Fig. 7 Z-X Plane view specification of redistribution layer 50 is different from the Fig. 7 Z-X Plane view specification of first circuit layer 114_120; and where the copper material specification of second circuit layer 148_146_142 is the same as the copper material specification of first circuit layer 114_120).
Regarding claim 3, Chen discloses a package substrate, wherein a surface of the first insulating layer is flush with a surface of the first circuit layer (Fig. 7 and ¶[0032_0034 & 0037] shows where the surface of first insulating layer 112 is flush with the surface of first circuit layer 114_120).
Regarding claim 5, Chen discloses a package substrate, wherein a coefficient of thermal expansion of the second circuit structure is greater than a coefficient of thermal expansion of the first circuit structure (Fig. 7 and ¶[0021-0022_0032-0033 & 0043] shows and indicates where the coefficient of thermal expansion of second circuit structure 140 is greater than the coefficient of thermal expansion of first circuit structure 114 {redistribution structure 140 formed of UBMs 146 and metallization layers 144, where UBMs 146 may be formed of the same copper material as the metallization layers 144, indicated in [0021 & 0043]; single seed layer of conductive material such as copper forms UBMLs 114, indicated in [0022 & 0032-0033]; therefore, the coefficient of thermal expansion of both copper layers of UBMs 146 and metallization layers 144 will have a greater coefficient of thermal expansion of a single copper layer of UBMLs 114}).
Conclusion
The FOLLOWING PRIOR ART is made of record and not relied upon, but considered pertinent to applicant's method independent claim 6:
Lin et al. (CN110581075A) meets every limitation in Independent Claim 6.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847