Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-34 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub # 2004/0223354).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Lee teaches a semiconductor device comprising: a precharge pulse generation circuit configured to generate a first precharge pulse and a second precharge pulse, based on a column pulse generated when a column operation including a write operation and a read operation is performed (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038 where precharge circuit 36, 37 generate precharge pulse for each bit line pair based on column pulse select circuit 33 and write read driver unit 35); and an input/output switching signal generation circuit configured to generate an input/output switching signal for connecting a first input/output line pair and a second input/output line pair to each other, based on the first precharge pulse and the second precharge pulse in a test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038 where transistors Mi, Mj inside input/output switching unit 34 connect first and second input/output pair line IO (E), IO (O)).
Even though Lee teaches read / write operation but silent exclusively about test mode. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lee where writing operation followed by reading the memory cell is required to test the cell and would be called test mode in order to verify the memory cell and to prevent speed degradation due to noise (see paragraph 0038).
Regarding claim 2, Lee teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Lee further teaches, wherein the precharge pulse generation circuit is configured to sequentially generate the first precharge pulse and the second precharge pulse after the column pulse is generated (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038).
Regarding claim 3, Lee teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Lee further teaches, wherein the precharge pulse generation circuit is configured to: generate the first precharge pulse after the column pulse is generated; and generate the second precharge pulse after the first precharge pulse is generated (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0028).
Regarding claim 4, Lee teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Lee further teaches, wherein the input/output switching signal generation circuit is configured to generate the input/output switching signal from a pre-switching signal, the first precharge pulse, and the second precharge pulse, based on a test mode signal (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0030).
Regarding claim 5, Lee teaches all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Lee further teaches, wherein the input/output switching signal generation circuit is configured to receive the test mode signal that is activated in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0035).
Regarding claim 6, Lee teaches all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Lee further teaches, wherein the input/output switching signal generation circuit is configured to: generate the pre-switching signal that is activated during a preset interval when the write operation is performed; and generate the pre-switching signal that is deactivated when the read operation is performed (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0032).
Regarding claim 7, Lee teaches all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Lee further teaches, wherein the input/output switching signal generation circuit is configured to generate a test column pulse, based on the first precharge pulse and the second precharge pulse in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0027).
Regarding claim 8, Lee teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Lee further teaches, wherein the input/output switching signal generation circuit is configured to generate the test column pulse from a time point at which the second precharge pulse is generated to a time point at which the first precharge pulse is generated in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0037).
Regarding claim 9, Lee teaches all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Lee further teaches, wherein the input/output switching signal generation circuit is configured to output the test column pulse as the input/output switching signal in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0032).
Regarding claim 10, Lee teaches all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Lee further teaches, wherein the input/output switching signal generation circuit is configured to output the pre-switching signal as the input/output switching signal when the test mode is not performed (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026).
Regarding claim 11, Lee teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Lee further teaches, further comprising a bank connected to the first input/output line pair and the second input/output line pair (see Fig.1-4 and paragraph 009-0014, 0016-0019).
Regarding claim 12, Lee teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Lee further teaches, further comprising an input/output switch connected between the first input/output line pair and the second input/output line pair, the input/output switch configured to be turned on based on the input/output switching signal (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0032).
Regarding claim 13, Lee teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Lee further teaches, further comprising: a first input/output line precharge circuit configured to precharge the first input/output line pair, based on the first precharge pulse; and a second input/output line precharge circuit configured to precharge the second input/output line pair, based on the second precharge pulse (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0033).
Regarding independent claim 14, Lee teaches a semiconductor device comprising: a first precharge pulse generation circuit configured to generate a first precharge pulse and a second precharge pulse, based on a first column pulse generated when a first column operation including a write operation and a read operation is performed on a first bank (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038 where precharge circuit 36, 37 generate precharge pulse for each bit line pair based on column pulse select circuit 33 and write read driver unit 35); a second precharge pulse generation circuit configured to generate a third precharge pulse and a fourth precharge pulse, based on a second column pulse generated when a second column operation including a write operation and a read operation is performed on a second bank (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038 where second precharge circuit 37 generate precharge pulse for each bit line pair based on column pulse generated from write read driver unit 35); and an input/output switching signal generation circuit configured to generate a first input/output switching signal for connecting a first input/output line pair and a second input/output line pair, based on the second column pulse and the second precharge pulse in a test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038 where transistors Mi, Mj inside input/output switching unit 34 connect first and second input/output pair line IO (E), IO (O)).
Even though Lee teaches read / write operation but silent exclusively about test mode. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lee where writing operation followed by reading the memory cell is required to test the cell and would be called test mode in order to verify the memory cell and to prevent speed degradation due to noise (see paragraph 0038).
Regarding claim 15, Lee teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Lee further teaches, wherein the first precharge pulse generation circuit is configured to sequentially generate the first precharge pulse and the second precharge pulse after the first column pulse is generated (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0036).
Regarding claim 16, Lee teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Lee further teaches, wherein the second precharge pulse generation circuit is configured to sequentially generate the third precharge pulse and the fourth precharge pulse after the second column pulse is generated (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0031).
Regarding claim 17, Lee teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Lee further teaches, wherein the first input/output switching signal generation circuit is configured to generate the first input/output switching signal from a first pre-switching signal, the second column pulse, and the second precharge pulse, based on a test mode signal (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0030).
Regarding claim 18, Lee teaches all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Lee further teaches, wherein the first input/output switching signal generation circuit is configured to: generate the first pre-switching signal that is activated during a preset interval when a write operation on the first bank is performed; and generate the first pre-switching signal that is deactivated when a read operation on the first bank is performed (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0032).
Regarding claim 19, Lee teaches all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Lee further teaches, wherein the first input/output switching signal generation circuit is configured to generate a first test column pulse, based on the second column pulse and the second precharge pulse in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0034).
Regarding claim 20, Lee teaches all claimed subject matter as applied in prior rejection of claim 19 on which this claim depends.
Lee further teaches, wherein the first input/output switching signal generation circuit is configured to generate the first test column pulse from a time point at which the second precharge pulse is generated to a time point at which the second column pulse is generated in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0037).
Regarding claim 21, Lee teaches all claimed subject matter as applied in prior rejection of claim 19 on which this claim depends.
Lee further teaches, wherein the first input/output switching signal generation circuit is configured to output the first test column pulse as the first input/output switching signal in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038).
Regarding claim 22, Lee teaches all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Lee further teaches, wherein the first input/output switching signal generation circuit is configured to output the first pre-switching signal as the first input/output switching signal when the test mode is not performed (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0029).
Regarding claim 23, Lee teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Lee further teaches, wherein the first bank is connected to the first input/output line pair and the second input/output line pair (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0030).
Regarding claim 24, Lee teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Lee further teaches, further comprising a first input/output switch connected between the first input/output line pair and the second input/output line pair, the first input/output switch configured to be turned on based on the first input/output switching signal (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0031).
Regarding claim 25, Lee teaches all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Lee further teaches, further comprising a second input/output switching signal generation circuit configured to generate a second input/output switching signal for connecting a third input/output line pair and the second input/output line pair to each other, based on the first column pulse and the fourth precharge pulse in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0032).
Regarding claim 26, Lee teaches all claimed subject matter as applied in prior rejection of claim 25 on which this claim depends.
Lee further teaches, wherein the second input/output switching signal generation circuit is configured to generate the second input/output switching signal from a second pre-switching signal, the first column pulse, and the fourth precharge pulse, based on a test mode signal (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0033).
Regarding claim 27, Lee teaches all claimed subject matter as applied in prior rejection of claim 26 on which this claim depends.
Lee further teaches, wherein the second input/output switching signal generation circuit is configured to: generate the second pre-switching signal that is activated during a preset interval when a write operation on the second bank is performed; and generate the second pre-switching signal that is deactivated when a read operation on the second bank is performed (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038).
Regarding claim 28, Lee teaches all claimed subject matter as applied in prior rejection of claim 26 on which this claim depends.
Lee further teaches, wherein the second input/output switching signal generation circuit is configured to generate a second test column pulse, based on the first column pulse and the fourth precharge pulse in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0028).
Regarding claim 29, Lee teaches all claimed subject matter as applied in prior rejection of claim 28 on which this claim depends.
Lee further teaches, wherein the second input/output switching signal generation circuit is configured to generate the second test column pulse from a time point at which the fourth precharge pulse is generate to a time point at which the first column pulse is generated in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0027).
Regarding claim 30, Lee teaches all claimed subject matter as applied in prior rejection of claim 28 on which this claim depends.
Lee further teaches, wherein the second input/output switching signal generation circuit is configured to output the second test column pulse as the second input/output switching signal in the test mode (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0035).
Regarding claim 31, Lee teaches all claimed subject matter as applied in prior rejection of claim 27 on which this claim depends.
Lee further teaches, wherein the second input/output switching signal generation circuit is configured to output the second pre-switching signal as the second input/output switching signal when the test mode is not performed (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0036).
Regarding claim 32, Lee teaches all claimed subject matter as applied in prior rejection of claim 25 on which this claim depends.
Lee further teaches, wherein the second bank is connected to the third input/output line pair and the second input/output line pair (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026).
Regarding claim 33, Lee teaches all claimed subject matter as applied in prior rejection of claim 25 on which this claim depends.
Lee further teaches, further comprising a second input/output switch connected between the third input/output line pair and the second input/output line pair, the second input/output switch configured to be turned on based on the second input/output switching signal (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0035).
Regarding claim 34, Lee teaches all claimed subject matter as applied in prior rejection of claim 25 on which this claim depends.
Lee further teaches, further comprising: a first input/output line precharge circuit configured to precharge the first input/output line pair, based on the first precharge pulse; a second input/output line precharge circuit configured to precharge the third input/output line pair, based on the third precharge pulse; a synthetic precharge pulse generating circuit configured to generate a synthetic precharge pulse, based on the second precharge pulse and the fourth precharge pulse; and a third input/output line precharge circuit configured to precharge the second input/output line pair, based on the synthetic precharge pulse (see Fig.1-4 and paragraph 009-0014, 0016-0019, 0026-0038).
Response to Arguments
Applicant's arguments filed 01/08/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 12 of remarks) that Lee fails to disclose, "an input/output switching signal generation circuit configured to generate an input/output switching signal that connects a first input/output line pair to a second input/output line pair based on the first precharge pulse and the second precharge pulse during a test mode". Examiner respectfully disagrees with this statement.
First, the limitation “connects” would be interpreted as electrical connection as also applicant agreed in remarks.
Second, the limitation “test mode” is broad where any reading operation to verify / test the stored data in memory cell would be considered as test mode.
In Fig. 3, paragraph 0027-0034, Lee teaches first precharge circuit 36 and second precharge circuit 37 generate first precharge signal and second precharge signal accordingly. Lee et al. also teach first I/O pair IO(E) pair and IO(O) pair line controlled by switching transistors M(E) and M(O) accordingly which are activated by another switching unit 33 (control the gate of switching transistors). So, unit 33 generates input/output switching signal for the switch unit 34.
During reading operation / test mode (specially see paragraph 0034), both even I/O (E) pair and ODD I/O (O) pair lines are electrically connected through control transistors where Mi, Mj transistors of unit 34 are turned on by the gate signal from unit 34. Based on precharge signal from unit 36 and 37, sense amp unit 35 alos activate to amplify the data signals from I/O pair lines and transmit the data to DIO line. Here, both I/O (E) and I/O (O) pair lines are electrically connected to single DIO line to transmit data through unit 38. So, Lee actually teach the limitation.
Claim 14 and all other dependent claims are rejected due to same reason above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824