Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 08/05/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 1-20 are pending and claims 11-20 were previously withdrawn. Claims 1, 2, 4, and 7 have been amended.
The amendment to the title has overcome the objection to the specification.
Response to Arguments
Applicant's arguments filed 08/05/2026 have been fully considered but they are not persuasive.
Applicant asserts regarding claim 1:
Suzuki does not teach "an opening extending from the conductive layer through the insulating laver to the base layer," as recited. Additionally, both Suzuki and Sakamoto fail to teach or fairly suggest that the opening is "sized and shaped to include a circuit chip disposed directly on the base laver," as recited by claim 1.
Examiner’s response:
Examiner agrees with the above assertion. However, the amendments necessitated an updated search. Based on the updated search, a new ground of rejection has been applied over new prior art, Karnezos et al. (US 6326678 B1; hereinafter “Karnezos”), Kodama et al. (US 20170141093 A1; hereinafter “Kodama”), Jeong et al. (US 20230142267 A1; hereinafter “Jeong”) as described below (see rejections of claim 1 below).
Applicant asserts regarding claim 2:
Moreover, claim 2 is allowable for additionally reciting "the top surface is parallel with respect to the bottom surface of the base layer," which Suzuki does not teach. Sakamoto, on the other hand, does not teach "a bottom surface of the opening is between a top surface and a bottom surface of the base layer."
Examiner’s response:
Examiner agrees with the above assertion. However, the amendments necessitated an updated search. Based on the updated search, a new ground of rejection has been applied over new prior art, Jeong et al. (US 20230142267 A1; hereinafter “Jeong”) as described below (see rejection of claim 2 below).
Applicant asserts regarding claim 4:
Further, claim 4 is allowable for additionally reciting "the depth of the opening is adjusted to match an impedance between the circuit chip and the conductive pattern." See specification at [0038]. Neither Suzuki nor Sakamoto teaches or fairly suggests such salient features.
Examiner’s response:
Examiner agrees with the above assertion. However, the amendments necessitated an updated search. Based on the updated search, a new ground of rejection has been applied over new prior art, Kodama et al. (US 20170141093 A1; hereinafter “Kodama”), Sakumoto et al. (US 20210327779 A1; hereinafter “Sakumoto”) and He et al. (US 20220304138 A1; hereinafter “He”) as described below (see rejection of claim 4 below).
Applicant asserts regarding claim 7:
Moreover, claim 7 is allowable for additionally reciting "each protruding portion has a round shape with a radius R of between about 25 µm to about 100 µm." See specification at [0046]. Neither Suzuki nor Sakamoto teaches or fairly suggests such salient features.
Examiner’s response:
Examiner agrees with the above assertion. However, the amendments necessitated an updated search. Based on the updated search, a new ground of rejection has been applied over new prior art, Karnezos et al. (US 6326678 B1; hereinafter “Karnezos”), Endou et al. (US 20060234023 A1; hereinafter “Endou”) as described below (see rejection of claim 7 below).
Therefore, claims 1-10 stand rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 has been amended adding the limitation: “the opening is sized and shaped to include a circuit chip disposed directly on the base layer”.
Applicant discloses in the PGPUB (US 20240297116 A1) the following:
[0040] FIG. 1A illustrates an exemplary integrated packaging device 100, according to some embodiments of the present disclosure. Integrated packaging device 100 may include a chip holder 102, a plurality of metal leads 104 attached to chip holder 102, and one or more connecting structures 103 attached to metal leads 104. A chip 105, e.g., one operating at high power and high frequency, may be placed in chip holder 102. In some embodiments, chip 105 is disposed in an opening 114 of chip holder 102. In some embodiments, chip 105 is connected to a base layer (e.g., a base layer 108 in FIG. 1B) by a die bonding material such as conductive epoxy, sintered Silver, sintered Gold, or eutectic solder.
However, there are no teachings in Applicant’s original disclosure for the circuit chip disposed directly on the base layer. Therefore, claim 1 fails to comply with the written description requirement and rejected under 112(a).
Dependent claims 2-10 do not rectify the deficiency and likewise rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6, 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karnezos et al. (US 6326678 B1; hereinafter “Karnezos”).
In re claim 1, Karnezos discloses, in figs. 2-6 (wherein fig. 2 seen in an upside-down view), an integrated packaging device 200 (C. 4, L. 33-60), comprising:
a base layer 201;
an insulating layer 213, 206 over and in contact with the base layer 201;
a conductive layer 205 over and in contact with the insulating layer 213, 206, the conductive layer comprising a conductive pattern; and
an opening 212 extending from the conductive layer 205 through the insulating layer 213, 206 to the base layer 201,
wherein the opening 212 is sized and shaped to include a circuit chip 211 disposed directly on the base layer 201 (as best understood, a circuit chip 211 disposed on the base layer 201 via a conductive epoxy 210 has been interpreted as a circuit chip 211 disposed directly on the base layer 201), and
the conductive pattern 205 surrounds the opening 212.
In re claim 3, Karnezos discloses in fig. 2 when seen in an upside-down view, the integrated packaging device of claim 1, wherein the insulating layer 213, 206 comprises epoxy (“Dielectric ring can be constructed from a ceramic material, an epoxy such as Ablefilm 564AKHM”; C. 4, L. 48-60), polytetrafluoroethylene (PTFE).
In re claim 6, Karnezos discloses, in figs. 2-6, The integrated packaging device of claim 1, wherein the opening 212 comprises a rectangular portion (fig. 4; a portion into which the chip 211 is disposed) and at least one protruding portion (fig. 4; corner protruding portions of the ceramic window 212 onto which interposer ring sections 208a-208d and tie bars 241a-241d are disposed; C. 5, L. 54-67 and C. 6, L. 1-18) in connection with a corner of the rectangular portion.
In re claim 8, Karnezos discloses in fig. 2 when seen in an upside-down view, the integrated packaging device of claim 1, wherein the base layer and the conductive layer each comprises copper (C. 4, L. 33-60).
Claim(s) 1, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kodama et al. (US 20170141093 A1; hereinafter “Kodama”).
In re claim 1, Kodama discloses, in figs. 1A-1B, an integrated packaging device, comprising:
a base layer 10 (¶18);
an insulating layer 32 over and in contact with the base layer 10 (¶20);
a conductive layer 36 over and in contact with the insulating layer 32 (¶20),
the conductive layer 36 comprising a conductive pattern 36, 36 (e.g., conductive layer 36 has two portions of conductive patterns on the left and right side of the device 18); and
an opening extending from the conductive layer through the insulating layer to the base layer (e.g., an opening which is delimited by layers 32, 36. Hereinafter “OPN”),
wherein the opening (OPN) is sized and shaped to include a circuit chip 18 disposed directly on the base layer 10 (as best understood, a circuit chip 18 disposed on the base layer 10 via a solder 15 has been interpreted as a circuit chip 18 disposed directly on the base layer 201) (¶18-19), and
the conductive pattern 36, 36 surrounds the opening.
In re claim 10, Kodama discloses, in figs. 1A-1B, the integrated packaging device of claim 1, further comprising:
a mask layer 34 (¶20) surrounding the opening (OPN) and separating an inner portion and an outer portion of the conductive pattern 36, 36 (the insulator 34 separates an inner portion and an outer portion of the conductive pattern 36, 36); and
a plurality of conductive leads 40 in contact with the outer portion of the conductive pattern 36, 36 (as shown in figs. 1A-1B, a plurality of conductive leads 40 in contact with the outer portion of the conductive pattern 36, 36).
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeong et al. (US 20230142267 A1; hereinafter “Jeong”).
In re claim 1, Jeong discloses, in fig. 1, an integrated packaging device, comprising:
a base layer (Base layer has been interpreted as layers comprising 150, bottom 112/114/116. Hereinafter “Base”) (¶16-17);
an insulating layer (middle and top resin based layers 112) (¶18, 32) over and in contact with the base layer (Base);
a conductive layer 120 (¶19) over and in contact with the insulating layer 112,
the conductive layer 120 comprising a conductive pattern 122, 122 (¶19-20); and
an opening CA (¶17, 25) extending from the conductive layer 120through the insulating layer to the base layer (Base),
wherein the opening CA is sized and shaped to include a circuit chip 130 disposed directly on the base layer (Base) (¶25), and
the conductive pattern 122, 122 surrounds the opening CA.
In re claim 2, Jeong discloses the integrated packaging device of claim 1 outlined above.
Jeong further discloses, in fig. 1, an integrated packaging device, wherein a bottom surface of the opening CA (¶17) is between a top surface and a bottom surface of the base layer (Base layer has been interpreted as layers comprising 150, bottom 112/114/116) (¶16-17), and
wherein the top surface (i.e., the top surface of the bottom layer 112) is parallel with respect to the bottom surface of the base layer (i.e., the bottom surface of the layer 152).
In re claim 3, Jeong discloses, in fig. 1, the integrated packaging device of claim 1, wherein the insulating layer 112 comprises epoxy (¶32), polytetrafluoroethylene (PTFE).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kodama, as applied to claim 1 above, and further in view of Sakumoto et al. (US 20210327779 A1; hereinafter “Sakumoto”) and He et al. (US 20220304138 A1; hereinafter “He”).
In re claim 4, Kodama discloses the integrated packaging device of claim 1,
Kodama does not expressly disclose wherein:
a depth of the opening is at least a sum of a thickness of the insulating layer, a thickness of the conductive layer, a thickness of the circuit chip, and a thickness of a bonding over the conductive layer, and
the depth of the opening is adjusted to match an impedance between the circuit chip and the conductive pattern.
In the same field of endeavor, Sakumoto discloses, in fig. 1, an integrated packaging device, wherein:
a depth of the opening is at least a sum of a thickness of an insulating layer 4, a thickness of a conductive layer (traces formed on layer 4), a thickness of the circuit chip 2, and a thickness of a bonding over the conductive layer 6 (¶14-16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Sakumoto into Kodama’s package.
One would have been motivated to do as He teaches a depth of the groove can enhance structural strength of the circuit board and the performance of the impedance matching circuit (¶77 and fig. 14 of He).
The combined teachings of Kodama, Sakumoto and He disclose the depth of the opening is adjusted to match an impedance between the circuit chip and the conductive pattern (¶77 and fig. 14 of He).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karnezos in view of Suzuki et al. (US 5977633 A; hereinafter “Suzuki”).
In re claim 5, Karnezos discloses the integrated packaging device of claim 1 outlined above.
Karnezos discloses, in figs. 2-6, a thickness of the base layer 201 is 0.09 inch (i.e., 2286 µm).
Karnezos does not expressly disclose:
a thickness of the base layer is between about 200 µm and about 1000 µm;
a thickness of the insulating layer is between about 200 µm and about 300 µm; and
a thickness of the conductive layer is between about 10 µm and about 50 µm.
In the same field of endeavor, Suzuki discloses in an upside-down view of figs. 2-3, the integrated packaging device of claim 1, wherein:
a thickness of the base layer 101 is between 150 μm to 250 μm (e.g., 0.15-0.25 mm; Col. 5, 4th paragraph), which overlaps the claimed range of about 200 μm and about 1000 μm;
and a thickness of the conductive layer 103 is about 10 μm and about 50 μm (e.g., 18-35 μm; Col. 5, 4th paragraph).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Suzuki and employ into Karnezos’s package and form a thickness of the base layer between about 200 μm and about 1000 μm in order to provide a semiconductor device structure which is high in efficiency of heat radiation and stabilizes the ground (or power supply) wiring mechanically and which enables visual inspection of the state of packaging, thus improving the reliability of mounting the package onto the mother board and hence lowering the manufacturing cost (Col. 2, last but one paragraph).
Furthermore, Suzuki discloses a thickness of the insulating layer 102 is between 20-55 μm (Col. 5, 4th paragraph). Suzuki further teaches the insulating layer 102 gives a high-temperature dielectric with strong mechanical stability and electrical properties over a wide temperature range, over its entire back (lower) surface except the dimpled portion (Col. 5, 4th paragraph).
Suzuki does not teach a thickness of the insulating layer 102 is between about 200 μm and about 300 μm.
However, it has been held to be within the general skill of a worker in the art to select a thickness for the insulating layer on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a thickness of the insulating layer of Karnezos between about 200 μm and about 300 μm to give a high-temperature dielectric with strong mechanical stability and electrical properties over a wide temperature range.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karnezos in view of Endou et al. (US 20060234023 A1; hereinafter “Endou”).
In re claim 7, Karnezos discloses the integrated packaging device of claim 6 outlined above.
Karnezos does not expressly disclose the integrated packaging device of claim 6, wherein the opening comprises four protruding portions each in connection with a corner of the rectangular portions and each protruding portion has a round shape with a radius R of between about 25 μm to about 100 μm.
In the same field of endeavor, Endou discloses, in figs. 1-7, an integrated packaging device, wherein an opening 11 comprises four protruding portions each in connection with a corner of the rectangular portions and each protruding portion has a round shape (as shown in fig. 2A, the opening 200 comprises four protruding portions each in connection with a corner of the rectangular portions and each protruding portion has a round shape) (¶114).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Endou into the package of Karnezos and form four protruding portions each in connection with a corner of the rectangular portions and each protruding portion has a round shape in order to alleviate generated stress and eliminate cracks formed in the package (¶114 of Endou).
Endou does not teach each protruding portion has a round shape with a radius R of between about 25 μm to about 100 μm.
However, it has been held to be within the general skill of a worker in the art to select a shape of the opening comprising four rounded corners on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select a round shape with a radius R of between about 25 μm to about 100 μm to alleviate generated stress and eliminate cracks formed in the package (¶114 of Endou).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kodama in view of Verhaverbeke et al. (US 20230148220 A1; hereinafter “Verhaverbeke”).
In re claim 9, Kodama discloses the integrated packaging device of claim 1 outlined above.
Kodama does not expressly disclose the package further comprising a plurality of conductive vias connecting a ground line of the conductive pattern and the base layer.
In the same field of endeavor, Verhaverbeke discloses, in figs. 18A-18B, an integrated packaging device, wherein the device comprising: a plurality of conductive vias 1444 (¶154) connecting a ground line of a conductive pattern 1812 and a base layer 1644 (¶150).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teachings of Verhaverbeke into the package of Kodama and connect the base with a ground line formed in the conductive pattern to provide an electromagnetic interference (EMI) shielding effect for dies disposed within openings (¶150 of Verhaverbeke).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
