DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 05/13/2026 is acknowledged.
Status of the Application
Claims 1-11 and 21-31 remain pending in this application. Acknowledgement is made of the amendment received 05/13/2026. Claims 12-20 are canceled, claim 10 is amended, and claims 21-31 are added for consideration.
Claim Objections
Claims 4, 9, 24, and 29 are objected to because of the following informalities:
Regarding claim 4, the claim recites “… between layers of first material …”, it should read “… between layers of a first material …”.
Regarding claim 9, the claim recites “… removing portions of second material via…”, it should read “… removing portions of the second material via…”.
Regarding claim 24, the claim recites “… between layers of first material …”, it should read “… between layers of a first material …”.
Regarding claim 29, the claim recites “… removing portions of second material via…”, it should read “… removing portions of the second material via…”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-8, 11, 21-28, and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amano et al (US 20220230917 A1, as disclosed in IDS dated 04/23/2026, hereafter Amano).
Regarding claim 1, Amano discloses: A method (Amano ¶0030), comprising:
forming a stack of material layers (Amano 32, 42, 46, ¶0049, 0051) over a substrate (Amano 8, ¶0035) of a memory die (Amano 700, ¶0034, 0037, 0041)(Amano fig 3A);
forming a plurality of cavities (Amano 71, ¶0062) through the stack of material layers (Amano fig 4A, 4B, ¶0062);
forming a merged cavity (Amano 79, fig 7A, 7B, ¶0073) through the stack of material layers at least in part by merging at least two cavities (Amano 71, fig 4B, 7B) of the plurality of cavities (Amano fig 7A, 7B, ¶0073, at least two 71 are merged to form 79); and
forming a conductor (Amano 78) through the stack of material layers based at least in part on forming one or more conductive materials (Amano ¶0099, “at least one conductive material … can be deposited in the backside trenches 79”) in the merged cavity (Amano fig 17, ¶0099).
Regarding claim 2, Amano discloses: The method of claim 1, further comprising:
forming a plurality of second cavities (Amano 41, 49, ¶0062, “memory openings 41”) through the stack of material layers (Amano 32, 42, 46)(Amano fig 4A, 4B, ¶0062); and
forming a plurality of memory cells (Amano 55, 58, 59, ¶0133, 0135-0136) based at least in part on forming a semiconductor material (Amano 55, 50, 52, 54, 56, 60, ¶0115, 0116, 0118, 0121, 0122) in the plurality of second cavities (Amano fig 19A-19G, 20A, ¶0114-0133),
wherein the conductor (Amano 78) is operable to electrically couple with at least a subset of the plurality of memory cells (Amano ¶0134, at least capable thereof, see MPEP 2114).
Regarding claim 3, Amano discloses: The method of claim 2, wherein the plurality of second cavities (Amano 41) are formed concurrently with forming the plurality of cavities (Amano 71)(Amano fig 4A, ¶0062).
Regarding claim 4, Amano discloses: The method of claim 2, further comprising:
forming a plurality of voids (Amano 43) based at least in part on removing respective portions of a second material (Amano 42) of the stack of material layers (Amano 32, 42, 46) from between layers of first material (Amano 32) of the stack of material layers (Amano fig 8, ¶0074-0077); and
forming a plurality of word lines (Amano 46, ¶0085)(Amano fig 9, ¶0081-0085) electrically coupled with the plurality of memory cells based at least in part on forming one or more second conductive materials in the plurality of voids (Amano fig 9, ¶0085),
wherein the conductor (Amano 78) is electrically coupled with at least one word line of the plurality of word lines (Amano fig 20A, at least indirectly via 58, 59, 10, 61).
Regarding claim 5, Amano discloses: The method of claim 1, wherein:
forming the at least two cavities (Amano 71, fig 4B, 7B) exposes a third conductive material (Amano 10, 61, ¶0036, 0045, 0078) between the stack of material layers (Amano 32, 42, 46) and the substrate (Amano 8)(Amano fig 2, 20A); and
forming the conductor comprises forming a conductive material of the one or more conductive materials (Amano ¶0099) in contact with the third conductive material (Amano fig 20A, ¶0078).
Regarding claim 6, Amano discloses: The method of claim 1, wherein the conductor (Amano 78) is electrically coupled with one or more transistors (Amano 710, 742, 746, 750, ¶0037) formed at least in part from a doped portion (Amano 9, ¶0035) of the substrate (Amano 8)(Amano fig 2, 20A, ¶0134 78 at least indirectly via 118, 788, 780).
Regarding claim 7, Amano discloses: The method of claim 1, wherein merging the at least two cavities comprises:
forming a plurality of voids between adjacent cavities of the at least two cavities (Amano 71) based at least in part on removing respective portions of a second material (Amano 32) of the stack of material layers (Amano 32, 42, 46) between layers of a first material (Amano 42) of the stack of material layers (Amano fig 7A, 7B, ¶0071-0073).
Regarding claim 8, Amano discloses: The method of claim 1, wherein merging the at least two cavities comprises:
removing respective portions of a first material (Amano 42) of the stack of material layers (Amano 32, 42, 46) and a second material (Amano 32) of the stack of material layers between adjacent cavities of the at least two cavities (Amano 71)(Amano fig 6, 7A, 7B, ¶0070-0073).
Regarding claim 11, Amano discloses: The method of claim 1, wherein the stack of material layers (Amano 32, 42, 46) comprises alternating layers of an oxide material (Amano 32, ¶0051, “silicon oxide”) and a nitride material (Amano 42, ¶0053, “silicon nitride”).
Regarding claim 21, Amano discloses: An apparatus formed by a process comprising:
forming a stack of material layers (Amano 32, 42, 46, ¶0049, 0051) over a substrate (Amano 8, ¶0035) of a memory die (Amano 700, ¶0034, 0037, 0041)(Amano fig 3A);
forming a plurality of cavities (Amano 71, ¶0062) through the stack of material layers (Amano fig 4A, 4B, ¶0062);
forming a merged cavity (Amano 79, fig 7A, 7B, ¶0073) through the stack of material layers at least in part by merging at least two cavities (Amano 71, fig 4B, 7B) of the plurality of cavities (Amano fig 7A, 7B, ¶0073, at least two 71 are merged to form 79); and
forming a conductor (Amano 78) through the stack of material layers based at least in part on forming one or more conductive materials (Amano ¶0099, “at least one conductive material … can be deposited in the backside trenches 79”) in the merged cavity (Amano fig 17, ¶0099).
Regarding claim 22, Amano discloses: The apparatus of claim 21, formed by the process further comprising:
forming a plurality of second cavities (Amano 41, 49, ¶0062, “memory openings 41”) through the stack of material layers (Amano 32, 42, 46)(Amano fig 4A, 4B, ¶0062); and
forming a plurality of memory cells (Amano 55, 58, 59, ¶0133, 0135-0136) based at least in part on forming a semiconductor material (Amano 55, 50, 52, 54, 56, 60, ¶0115, 0116, 0118, 0121, 0122) in the plurality of second cavities (Amano fig 19A-19G, 20A, ¶0114-0133),
wherein the conductor (Amano 78) is operable to electrically couple with at least a subset of the plurality of memory cells (Amano ¶0134, at least capable thereof, see MPEP 2114).
Regarding claim 23, Amano discloses: The apparatus of claim 22, wherein the plurality of second cavities (Amano 41) are formed concurrently with forming the plurality of cavities (Amano 71)(Amano fig 4A, ¶0062).
Regarding claim 24, Amano discloses: The apparatus of claim 22, formed by the process further comprising:
forming a plurality of voids (Amano 43) based at least in part on removing respective portions of a second material (Amano 42) of the stack of material layers (Amano 32, 42, 46) from between layers of first material (Amano 32) of the stack of material layers (Amano fig 8, ¶0074-0077); and
forming a plurality of word lines (Amano 46, ¶0085)(Amano fig 9, ¶0081-0085) electrically coupled with the plurality of memory cells based at least in part on forming one or more second conductive materials in the plurality of voids (Amano fig 9, ¶0085),
wherein the conductor (Amano 78) is electrically coupled with at least one word line of the plurality of word lines (Amano fig 20A, at least indirectly via 58, 59, 10, 61).
Regarding claim 25, Amano discloses: The apparatus of claim 21, wherein:
forming the at least two cavities (Amano 71, fig 4B, 7B) exposes a third conductive material (Amano 10, 61, ¶0036, 0045, 0078) between the stack of material layers (Amano 32, 42, 46) and the substrate (Amano 8)(Amano fig 2, 20A); and
forming the conductor comprises forming a conductive material of the one or more conductive materials (Amano ¶0099) in contact with the third conductive material (Amano fig 20A, ¶0078).
Regarding claim 26, Amano discloses: The apparatus of claim 21, wherein the conductor (Amano 78) is electrically coupled with one or more transistors (Amano 710, 742, 746, 750, ¶0037) formed at least in part from a doped portion (Amano 9, ¶0035) of the substrate (Amano 8)(Amano fig 2, 20A, ¶0134 78 at least indirectly via 118, 788, 780).
Regarding claim 27, Amano discloses: The apparatus of claim 21, wherein merging the at least two cavities comprises:
forming a plurality of voids between adjacent cavities of the at least two cavities (Amano 71) based at least in part on removing respective portions of a second material (Amano 32) of the stack of material layers (Amano 32, 42, 46) between layers of a first material (Amano 42) of the stack of material layers (Amano fig 7A, 7B, ¶0071-0073).
Regarding claim 28, Amano discloses: The apparatus of claim 21, wherein merging the at least two cavities comprises:
removing respective portions of a first material (Amano 42) of the stack of material layers (Amano 32, 42, 46) and a second material (Amano 32) of the stack of material layers between adjacent cavities of the at least two cavities (Amano 71)(Amano fig 6, 7A, 7B, ¶0070-0073).
Regarding claim 31, Amano discloses: The apparatus of claim 21, wherein the stack of material layers (Amano 32, 42, 46) comprises alternating layers of an oxide material (Amano 32, ¶0051, “silicon oxide”) and a nitride material (Amano 42, ¶0053, “silicon nitride”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 10, 29, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Amano et al (US 20220230917 A1, as disclosed in IDS dated 04/23/2026, hereafter Amano) in view of Matsuno et al (US 20220352197 A1, hereafter Matsuno).
Regarding claim 9, Amano discloses: The method of claim 1, further comprising:
forming a sacrificial material (Amano 73, ¶0068) in the plurality of cavities (Amano 71)(Amano fig 4A, 5A, ¶0068-0069);
removing the sacrificial material from the at least two second cavities of the plurality of cavities (Amano 71)(Amano fig 6, ¶0070-0071);
removing the sacrificial material from the at least two cavities of the plurality of cavities (Amano 71)(Amano fig 6, ¶0070-0071, removal of 73 from 71 empties both subsets of the plurality of cavities);
removing portions of a second material (Amano 42) via the at least two cavities (Amano fig 8, ¶0074-0077);
forming a conductive material (Amano 78) of the one or more conductive materials (Amano ¶0099)(Amano fig 17).
Amano does not teach: recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers;
forming portions of the first material over the exposed sidewalls of the second material;
removing portions of a second material via the at least two cavities to expose sidewalls of portions of a first material; and
forming a conductive material of the one or more conductive materials in contact with the portions of the first material.
Matsuno, in the same field of endeavor of semiconductor device manufacturing, teaches:
recessing a second material (Matsuno 42, ¶0157, “silicon nitride”) of a stack of material layers (Matsuno 32, 42, fig 3) via at least two second cavities (Matsuno 19B, fig 11B) to expose sidewalls of the second material between layers of a first material (Matsuno 32, ¶0157, “silicon oxide”) of the stack of material layers (Matsuno fig 11B, sidewall of 119);
forming portions of the first material (Matsuno 130, 130L, ¶0158, “silicon oxide”) over the exposed sidewalls of the second material (Matsuno fig 11C, ¶0158-0160);
removing portions of a second material via at least two cavities (Matsuno 79) to expose sidewalls of portions of a first material (Matsuno fig 19F, ¶0195-0197); and
forming a conductive material of the one or more conductive materials in contact with the portions of the first material (Matsuno ¶0199-0201).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amano to include “recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers; forming portions of the first material over the exposed sidewalls of the second material; removing portions of a second material via the at least two cavities to expose sidewalls of portions of a first material; and forming a conductive material of the one or more conductive materials in contact with the portions of the first material”, as taught by Matsuno, in order to prevent a short circuit between the conductive material and word lines, thereby improving device reliability (Matsuno ¶0232).
Regarding claim 10, Amano discloses: The method of claim 1, further comprising:
forming a sacrificial material (Amano 73, ¶0068) in the plurality of cavities (Amano 71)(Amano fig 4A, 5A, ¶0068-0069);
removing the sacrificial material from the at least two cavities of the plurality of cavities (Amano fig 6, ¶0070-0071); and
forming a conductive material (Amano 78) of the one or more conductive materials (Amano ¶0099) in contact with the portions of the first material (Amano fig 17).
Amano does not teach: recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers;
forming portions of the first material over the exposed sidewalls of the second material.
Matsuno, in the same field of endeavor of semiconductor device manufacturing, teaches:
recessing a second material (Matsuno 42, ¶0157, “silicon nitride”) of a stack of material layers (Matsuno 32, 42, fig 3) via at least two cavities (Matsuno 19B, fig 11B) to expose sidewalls of the second material between layers of a first material (Matsuno 32, ¶0157, “silicon oxide”) of the stack of material layers (Matsuno fig 11B, sidewall of 119);
forming portions of the first material (Matsuno 130, 130L, ¶0158, “silicon oxide”) over the exposed sidewalls of the second material (Matsuno fig 11C, ¶0158-0160).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amano to include “recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers; forming portions of the first material over the exposed sidewalls of the second material”, as taught by Matsuno, in order to prevent a short circuit between the conductive material and word lines, thereby improving device reliability (Matsuno ¶0232).
Regarding claim 29, Amano discloses: The apparatus of claim 21, formed by the process further comprising:
forming a sacrificial material (Amano 73, ¶0068) in the plurality of cavities (Amano 71)(Amano fig 4A, 5A, ¶0068-0069);
removing the sacrificial material from the at least two second cavities of the plurality of cavities (Amano 71)(Amano fig 6, ¶0070-0071);
removing the sacrificial material from the at least two cavities of the plurality of cavities (Amano 71)(Amano fig 6, ¶0070-0071, removal of 73 from 71 empties both subsets of the plurality of cavities);
removing portions of a second material (Amano 42) via the at least two cavities (Amano fig 8, ¶0074-0077);
forming a conductive material (Amano 78) of the one or more conductive materials (Amano ¶0099)(Amano fig 17).
Amano does not teach: recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers;
forming portions of the first material over the exposed sidewalls of the second material;
removing portions of a second material via the at least two cavities to expose sidewalls of portions of a first material; and
forming a conductive material of the one or more conductive materials in contact with the portions of the first material.
Matsuno, in the same field of endeavor of semiconductor device manufacturing, teaches:
recessing a second material (Matsuno 42, ¶0157, “silicon nitride”) of a stack of material layers (Matsuno 32, 42, fig 3) via at least two second cavities (Matsuno 19B, fig 11B) to expose sidewalls of the second material between layers of a first material (Matsuno 32, ¶0157, “silicon oxide”) of the stack of material layers (Matsuno fig 11B, sidewall of 119);
forming portions of the first material (Matsuno 130, 130L, ¶0158, “silicon oxide”) over the exposed sidewalls of the second material (Matsuno fig 11C, ¶0158-0160);
removing portions of a second material via at least two cavities (Matsuno 79) to expose sidewalls of portions of a first material (Matsuno fig 19F, ¶0195-0197); and
forming a conductive material of the one or more conductive materials in contact with the portions of the first material (Matsuno ¶0199-0201).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amano to include “recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers; forming portions of the first material over the exposed sidewalls of the second material; removing portions of a second material via the at least two cavities to expose sidewalls of portions of a first material; and forming a conductive material of the one or more conductive materials in contact with the portions of the first material”, as taught by Matsuno, in order to prevent a short circuit between the conductive material and word lines, thereby improving device reliability (Matsuno ¶0232).
Regarding claim 30, Amano discloses: The apparatus of claim 21, formed by the process further comprising:
forming a sacrificial material (Amano 73, ¶0068) in the plurality of cavities (Amano 71)(Amano fig 4A, 5A, ¶0068-0069);
removing the sacrificial material from the at least two cavities of the plurality of cavities (Amano fig 6, ¶0070-0071); and
forming a conductive material (Amano 78) of the one or more conductive materials (Amano ¶0099) in contact with the portions of the first material (Amano fig 17).
Amano does not teach: recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers;
forming portions of the first material over the exposed sidewalls of the second material.
Matsuno, in the same field of endeavor of semiconductor device manufacturing, teaches:
recessing a second material (Matsuno 42, ¶0157, “silicon nitride”) of a stack of material layers (Matsuno 32, 42, fig 3) via at least two cavities (Matsuno 19B, fig 11B) to expose sidewalls of the second material between layers of a first material (Matsuno 32, ¶0157, “silicon oxide”) of the stack of material layers (Matsuno fig 11B, sidewall of 119);
forming portions of the first material (Matsuno 130, 130L, ¶0158, “silicon oxide”) over the exposed sidewalls of the second material (Matsuno fig 11C, ¶0158-0160).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Amano to include “recessing a second material of the stack of material layers via the at least two cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers; forming portions of the first material over the exposed sidewalls of the second material”, as taught by Matsuno, in order to prevent a short circuit between the conductive material and word lines, thereby improving device reliability (Matsuno ¶0232).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Terasawa et al (US 20190280001 A1) is cited as an example of an analogous method.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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