DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/14/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 8-9, 11-13, and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Then et al. US 2023/0090106.
Re claim 1, Then teaches a field effect transistor (fig3) integrated within an associated transistor area (area of GaN transistor 300, fig3, [91]), the field effect transistor comprising transistor contacts having a contact configuration of cascoded contact fingers (228, 208, 302 and 232, fig3, [83, 92]) including a source contact finger (228, fig3, [83]), a drain contact finger (232, fig3, [83]), a first gate contact finger (208, fig3, [92]) provided between the source contact finger (228, fig3, [83]) and the drain contact finger (232, fig3, [83]), and a second gate contact finger (302, fig3, [91]) provided between the source contact finger (228, fig3, [83]) and the drain contact finger (232, fig3, [83]).
Re claim 3, Then teaches the field effect transistor of claim 1 wherein the first gate contact finger (208 with gate length Lg, fig3, [91]) has a different shape than the second gate contact finger (302 with gate length Lg2, fig3, [91]).
Re claim 4, Then teaches the field effect transistor of claim 1 wherein the first gate contact finger (208 with gate length Lg, fig3, [91]) has a different channel length than the second gate contact finger (302 with gate length Lg2, fig3, [91]).
Re claim 5, Then teaches the field effect transistor of claim 1 wherein at least one of the first gate contact finger (208, fig3, [91]) and the second gate contact finger (302, fig3, [91]) has a T-shape.
Re claim 8, Then teaches the field effect transistor of claim 1 wherein the first gate contact finger (208, fig3, [92]) is arranged closer to the source contact finger (228, fig3, [83]) than the second gate contact finger (302, fig3, [91]), and the second gate contact finger (302, fig3, [91]) is arranged closer to the drain contact finger (232, fig3, [83]) than the first gate contact finger (208, fig3, [92]).
Re claim 9, Then teaches a power amplifier (fig3/4) comprising at least one field effect transistor (GaN transistor 300 in fig3) integrated within an associated transistor area (area of GaN transistor 300, fig3, [91]), the at least one field effect transistor having transistor contacts with a contact configuration of cascoded contact fingers (228, 208, 302 and 232, fig3, [83, 92]) including a source contact finger (228, fig3, [83]), a drain contact finger (232, fig3, [83]), a first gate contact finger (208, fig3, [92]) provided between the source contact finger (228, fig3, [83]) and the drain contact finger (232, fig3, [83]), and a second gate contact finger (302, fig3, [91]) provided between the source contact finger (228, fig3, [83]) and the drain contact finger (232, fig3, [83]).
Re claim 11, Then teaches the power amplifier of claim 9 wherein the first gate contact finger (208 with gate length Lg, fig3, [91]) has a different shape than the second gate contact finger (302 with gate length Lg2, fig3, [91]).
Re claim 12, Then teaches the power amplifier of claim 9 wherein the first gate contact finger (208 with gate length Lg, fig3, [91]) has a different channel length than the second gate contact finger (302 with gate length Lg2, fig3, [91]).
Re claim 13, Then teaches the power amplifier of claim 9 wherein at least one of the first gate contact finger (208, fig3, [91]) and the second gate contact finger (302, fig3, [91]) has a T-shape.
Re claim 16, Then teaches the power amplifier of claim 9 wherein the first gate contact finger (208, fig3, [92]) is arranged closer to the source contact finger (228, fig3, [83]) than the second gate contact finger (302, fig3, [91]), and the second gate contact finger (302, fig3, [91]) is arranged closer to the drain contact finger (232, fig3, [83]) than the first gate contact finger (208, fig3, [91]).
Re claim 17, Then teaches the power amplifier of claim 9 wherein the transistor contacts include a first pad (282 over 208, fig3, [89]) for external bias connected to the first gate contact finger (208, fig3, [92]).
Re claim 18, Then teaches the power amplifier of claim 9 wherein the transistor contacts include a second pad (282 over 302, fig3, [89]) for external bias connected to the second gate contact finger (302, fig3, [92]).
Re claim 19, Then teaches the power amplifier of claim 9 wherein the transistor contacts include a source connected field plate (416 connected with source 410, fig4, [97]).
Re claim 20, Then teaches a wireless device (fig12) comprising:
a transceiver configured to process radio frequency signals (1200, fig12, [41, 152]); and
a radio frequency module (GaN transistor 300, fig3, [91]) including at least one field effect transistor integrated within an associated transistor area (area of GaN transistor 300, fig3, [91]) and having a contact configuration of cascoded contact fingers (228, 208, 302 and 232, fig3, [83, 92]) including a first gate contact finger (208, fig3, [92]) provided between a source contact finger (228, fig3, [83]) and a drain contact finger (232, fig3, [83]), and a second gate contact finger (302, fig3, [92]) provided between the source contact finger (228, fig3, [83]) and the drain contact finger (232, fig3, [83]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Then et al. US 2023/0090106 in view of Wang US 2008/0157222.
Re claim 2, Then does not explicitly show the field effect transistor of claim 1 wherein the cascoded contact fingers of the contact configuration have a rectangular shape.
Wang teaches wherein the cascoded contact fingers of the contact configuration have a rectangular shape (fig3 and 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Then and Wang to arrange the electrode contacts as in fig3 of Wang. The motivation to do so is to reduce layout area and parasitic capacitance (Wang, [17]).
Re claim 10, Then does not explicitly show the power amplifier of claim 9 wherein the cascoded contact fingers of the contact configuration have a rectangular shape.
Wang teaches wherein the cascoded contact fingers of the contact configuration have a rectangular shape (fig3 and 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Then and Wang to arrange the electrode contacts as in fig3 of Wang. The motivation to do so is to reduce layout area and parasitic capacitance (Wang, [17]).
Claim(s) 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Then et al. US 2023/0090106 in view of Wei et al. US 2019/0199289.
Re claim 6, Then does not explicitly show the field effect transistor of claim 1 wherein the transistor contacts include a source contact located on a back side of a die, the source contact connected by a through wafer via (TWV) to the source contact finger.
Wei teaches a source contact (511, fig5, [31]) located on a back side of a die (500, fig5), the source contact connected by a through wafer via (TWV) (520, fig5, [31]) to the source contact finger (534, fig5, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Then and Wei to form through wafer via connected with source 228. The motivation to do so is to reduce layout area and parasitic capacitance in the active area.
Re claim 14, Then does not explicitly show the power amplifier of claim 9 wherein the transistor contacts include a source contact located on a back side of a die, the source contact connected by a through wafer via, TWV, to the source contact finger.
Wei teaches a source contact (511, fig5, [31]) located on a back side of a die (500, fig5), the source contact connected by a through wafer via (TWV) (520, fig5, [31]) to the source contact finger (534, fig5, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Then and Wei to form through wafer via connected with source 228. The motivation to do so is to reduce layout area and parasitic capacitance in the active area.
Claim(s) 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Then et al. US 2023/0090106 in view of Miura et al. US 2018/0097070.
Re claim 7, Then does not explicitly show the field effect transistor of claim 1 wherein the transistor contacts include a metal-insulator-metal (MIM) capacitor arranged between the source contact finger and a second gate contact including the second gate contact finger.
Miura teaches the transistor contacts include a metal-insulator-metal (MIM) capacitor (MIM of GE1 and GBL1, fig1 and 2, [79]) arranged over gate electrode (GE1, fig1, [79]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Then and Miura to form an MIM section overlap with gate electrode. The motivation to do so is to suppress gate overvoltage and maintain stable operating characteristic (Miura, [84, 88]).
Then in view of Miura teaches wherein the transistor contacts include a metal-insulator-metal (MIM) capacitor (Then, MIM as in Miura formed in region with 208, fig2) arranged between the source contact finger (Then, 228, fig3, [83]) and a second gate contact including the second gate contact finger (Then, 302, fig3, [91]).
Re claim 15, Then does not explicitly show the power amplifier of claim 9 wherein the transistor contacts include a metal-insulator-metal, MIM, capacitor arranged between the source contact finger and a second gate contact including the second gate contact finger.
Miura teaches the transistor contacts include a metal-insulator-metal (MIM) capacitor (MIM of GE1 and GBL1, fig1 and 2, [79]) arranged over gate electrode (GE1, fig1, [79]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Then and Miura to form an MIM section overlap with gate electrode. The motivation to do so is to suppress gate overvoltage and maintain stable operating characteristic (Miura, [84, 88]).
Then in view of Miura teaches wherein the transistor contacts include a metal-insulator-metal (MIM) capacitor (Then, MIM as in Miura formed in region with 208, fig2) arranged between the source contact finger (Then, 228, fig3, [83]) and a second gate contact including the second gate contact finger (Then, 302, fig3, [91]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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