DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 06/12/2026. Claims 1, 7, 8, 14, and 15 are amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 7-12, 14, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al (US 20190189681 A1, hereafter Chae) in view of Chae et al (US 20190164945 A1, hereafter Chae-945).
Regarding claim 1, Chae, in at least one embodiment, teaches: A display apparatus (Chae 200, 2110, fig 1, 35, 41, 46, 59B, ¶0298-0301, 0360-0365, 0389, 0465), comprising:
a circuit board (Chae 200, 10, 351, ¶0143, 0298-0301, there appears to be a typographical error in fig 35, it appears that “210” should read “200”); and
a light source (Chae 220, 230, 240, 20, 30, 40, fig 35, 46, 1, ¶0146, 0299) connected to the circuit board (Chae fig 1, 35, 46, 59B, ¶0144, 0300, 0468), the light source including:
a first light emitting device (Chae 220, 20, ¶0302, 0304);
a second light emitting device (Chae 230, 30, ¶0302, 0304) disposed over the first light emitting device (Chae fig 35, 46, 1, ¶0304); and
a third light emitting device (Chae 240, 40, ¶0302, 0304) disposed over the second light emitting device (Chae fig 35, 46, 1, ¶0304), wherein:
the first light emitting device includes a first light emission stack (Chae 225, 223, 221, fig 36A, 36B, ¶0311-0312) configured to generate a light having a first peak wavelength (Chae L1, ¶0146, 0302-0303, 0312, “emitting a red light”);
the second light emitting device includes a second light emission stack (Chae 231, 233, 235, fig 36A, 36B, ¶0315) configured to generate a light having a second peak wavelength (Chae L2, ¶0146, 0302-0303, 0315, “emitting a green light”) that is shorter than the first peak wavelength (Chae ¶0030, 0146, “light may have a shorter wavelength band, … from the first color light L1 toward the third color light L3”);
the third light emitting device includes a third light emission stack (Chae 241, 243, 245, fig 36A, 36B, ¶0319) configured to generate a light having a third peak wavelength (Chae L3, ¶0146, 0302-0303, 0319, “emitting a blue light”) that is shorter than the second peak wavelength (Chae ¶0030, 0146, “light may have a shorter wavelength band, … from the first color light L1 toward the third color light L3”);
an area occupied by the first light emission stack is greater than each of an area occupied by the second light emission stack and an area occupied by the third light emission stack (Chae fig 46, ¶0407, “the area of … 230 may be smaller than the area of … 220”, ¶0410, “The area of … 240 may be smaller than the area of … 230”, therefore 220 has an area greater than 230, and 230 has an area greater than 240).
Chae does not explicitly teach: opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view.
Chae-945, in the same field of endeavor of semiconductor device manufacturing, teaches: a third light emission stack (Chae-945 543, ¶0726) disposed over a second light emission stack (Chae-945 533, ¶0726)(Chae-945 fig 64-C, ¶0727); wherein
opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view (Chae-945, ¶0727, 0743, fig 59, 63, 64A-C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify an area of the third light emission stack of Chae, such that “opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view”, as taught by Chae-945, in order to leave a peripheral region of the second light emission stack uncovered by the third light emissions stack, thereby reducing and/or preventing light loss of the second emission stack (Chae-945 ¶0728-0729).
Regarding claim 2, Chae in view of Chae-945 teaches: The display apparatus of claim 1, wherein:
the first light emission stack (Chae 225, 223, 221) includes an arsenic (Chae ¶0313, “aluminum gallium arsenide (AlGaAs)”) or phosphide-based semiconductor layer (Chae ¶0313, “gallium arsenide phosphide (GaAsP)”); and
the second (Chae 231, 233, 235) and third light emission stacks (Chae 241, 243, 245) include a nitride-based semiconductor layer (Chae ¶0315, “230 … indium gallium nitride (InGaN), gallium nitride (GaN)”, ¶0319, “240 … GaN, InGaN”).
Regarding claim 3, Chae in view of Chae-945 teaches: The display apparatus of claim 1, wherein the second light emission stack (Chae 231, 233, 235) and the third light emission stack (Chae 241, 243, 245) are stacked in a vertical direction (Chae ¶0300-0302, fig 35, 36A, 36B, 46).
Regarding claim 4, Chae in view of Chae-945, in at least one embodiment, teaches: The display apparatus of claim 1, further comprising an adhesive layer (Chae 60c, ¶0154, 0245) coupling the second light emission stack (Chae 231, 233, 235) and the third light emission stack (Chae 241, 243, 245)(Chae ¶0153, fig 2A).
Regarding claim 5, Chae in view of Chae-945 teaches: The display apparatus of claim 1, wherein the second light emitting device (Chae 230, 30) includes an electrode pad (Chae 235p, 245p, ¶0324) electrically connecting the second (Chae 231, 233, 235) and third light emission stacks (Chae 241, 243, 245)(Chae fig 46, ¶0325).
Regarding claim 7, Chae in view of Chae-945 teaches: The display apparatus of claim 1, wherein a luminous intensity of the first light emission stack (Chae 225, 223, 221) is lower than a luminous intensity of the second light emission stack (Chae 231, 233, 235)(Chae ¶0358 “light intensities, which may cause a difference in visibility … a red color … lower visibility than a green color”, ¶0472-0473).
Regarding claim 8, Chae, in at least one embodiment, teaches: A display apparatus (Chae 200, 2110, fig 1, 35, 41, 46, 59B, ¶0298-0301, 0360-0365, 0389, 0465), comprising:
a circuit board (Chae 200, 10, 351, ¶0143, 0298-0301, there appears to be a typographical error in fig 35, it appears that “210” should read “200”); and
a light source (Chae 220, 230, 240, 20, 30, 40, fig 35, 46, 1, ¶0146, 0299) connected to the circuit board (Chae fig 1, 35, 46, 59B, ¶0144, 0300, 0468), the light source including:
a first light emitting device (Chae 220, 20, ¶0302, 0304);
a second light emitting device (Chae 230, 30, ¶0302, 0304) disposed over the first light emitting device (Chae fig 35, 46, 1, ¶0304); and
a third light emitting device (Chae 240, 40, ¶0302, 0304) disposed over the second light emitting device (Chae fig 35, 46, 1, ¶0304), wherein:
the first light emitting device includes a first light emission stack (Chae 225, 223, 221, fig 36A, 36B, ¶0311-0312) configured to generate a light having a first peak wavelength (Chae L1, ¶0146, 0302-0303, 0312, “emitting a red light”);
the second light emitting device includes a second light emission stack (Chae 231, 233, 235, fig 36A, 36B, ¶0315) configured to generate a light having a second peak wavelength (Chae L2, ¶0146, 0302-0303, 0315, “emitting a green light”) that is shorter than the first peak wavelength (Chae ¶0030, 0146, “light may have a shorter wavelength band, … from the first color light L1 toward the third color light L3”);
the third light emitting device includes a third light emission stack (Chae 241, 243, 245, fig 36A, 36B, ¶0319) configured to generate a light having a third peak wavelength (Chae L3, ¶0146, 0302-0303, 0319, “emitting a blue light”) that is shorter than the second peak wavelength (Chae ¶0030, 0146, “light may have a shorter wavelength band, … from the first color light L1 toward the third color light L3”);
a width of the first light emission stack is greater than each of a width of the second light emission stack and a width of the third light emission stack (Chae fig 46, ¶0407, “the area of … 230 may be smaller than the area of … 220”, ¶0410, “The area of … 240 may be smaller than the area of … 230”, ¶0392, “a quadrangular shape”, for a quadrangular stack, having a greater area necessarily means a greater width, therefore 220 has an width greater than 230, and 230 has an width greater than 240).
Chae does not explicitly teach: opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view.
Chae-945, in the same field of endeavor of semiconductor device manufacturing, teaches: a third light emission stack (Chae-945 543, ¶0726) disposed over a second light emission stack (Chae-945 533, ¶0726)(Chae-945 fig 64-C, ¶0727); wherein
opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view (Chae-945, ¶0727, 0743, fig 59, 63, 64A-C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify an area of the third light emission stack of Chae, such that “opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view”, as taught by Chae-945, in order to leave a peripheral region of the second light emission stack uncovered by the third light emissions stack, thereby reducing and/or preventing light loss of the second emission stack (Chae-945 ¶0728-0729).
Regarding claim 9, Chae in view of Chae-945 teaches: The display apparatus of claim 8, wherein:
the first light emission stack (Chae 225, 223, 221) includes an arsenic (Chae ¶0313, “aluminum gallium arsenide (AlGaAs)”) or phosphide-based semiconductor layer (Chae ¶0313, “gallium arsenide phosphide (GaAsP)”); and
the second (Chae 231, 233, 235) and third light emission stacks (Chae 241, 243, 245) include a nitride-based semiconductor layer (Chae ¶0315, “230 … indium gallium nitride (InGaN), gallium nitride (GaN)”, ¶0319, “240 … GaN, InGaN”).
Regarding claim 10, Chae in view of Chae-945 teaches: The display apparatus of claim 8, wherein the second light emission stack (Chae 231, 233, 235) and the third light emission stack (Chae 241, 243, 245) are stacked in a vertical direction (Chae ¶0300-0302, fig 35, 36A, 36B, 46).
Regarding claim 11, Chae in view of Chae-945, in at least one embodiment, teaches: The display apparatus of claim 8, further comprising an adhesive layer (Chae 60c, ¶0154, 0245) coupling the second light emission stack (Chae 231, 233, 235) and the third light emission stack (Chae 241, 243, 245)(Chae ¶0153, fig 2A).
Regarding claim 12, Chae in view of Chae-945 teaches: The display apparatus of claim 8, wherein the second light emitting device (Chae 230, 30) includes an electrode pad (Chae 235p, 245p, ¶0324) electrically connecting the second (Chae 231, 233, 235) and third light emission stacks (Chae 241, 243, 245)(Chae fig 46, ¶0325).
Regarding claim 14, Chae in view of Chae-945 teaches: The display apparatus of claim 8, wherein a luminous intensity of the first light emission stack (Chae 225, 223, 221) is lower than a luminous intensity of the second light emission stack (Chae 231, 233, 235)(Chae ¶0358 “light intensities, which may cause a difference in visibility … a red color … lower visibility than a green color”, ¶0472-0473).
Regarding claim 15, Chae teaches: A display apparatus (Chae 200, 2110, fig 1, 35, 41, 46, 59B, ¶0298-0301, 0360-0365, 0389, 0465), comprising:
a circuit board (Chae 200, 10, 351, ¶0143, 0298-0301, there appears to be a typographical error in fig 35, it appears that “210” should read “200”); and
a light source (Chae 220, 230, 240, 20, 30, 40, fig 35, 46, 1, ¶0146, 0299) connected to the circuit board (Chae fig 1, 35, 46, 59B, ¶0144, 0300, 0468), the light source including:
a first light emitting device (Chae 220, 20, ¶0302, 0304);
a second light emitting device (Chae 230, 30, ¶0302, 0304) disposed adjacent to the first light emitting device (Chae fig 35, 46, 1, ¶0304, at least vertically adjacent); and
a third light emitting device (Chae 240, 40, ¶0302, 0304) disposed adjacent to the second light emitting device (Chae fig 35, 46, 1, ¶0304, at least vertically adjacent), wherein:
the first light emitting device includes a first light emission stack (Chae 225, 223, 221, fig 36A, 36B, ¶0311-0312) configured to generate a light having a first peak wavelength (Chae L1, ¶0146, 0302-0303, 0312, “emitting a red light”);
the second light emitting device includes a second light emission stack (Chae 231, 233, 235, fig 36A, 36B, ¶0315) configured to generate a light having a second peak wavelength (Chae L2, ¶0146, 0302-0303, 0315, “emitting a green light”) that is shorter than the first peak wavelength (Chae ¶0030, 0146, “light may have a shorter wavelength band, … from the first color light L1 toward the third color light L3”);
the third light emitting device includes a third light emission stack (Chae 241, 243, 245, fig 36A, 36B, ¶0319) configured to generate a light having a third peak wavelength (Chae L3, ¶0146, 0302-0303, 0319, “emitting a blue light”) that is shorter than the second peak wavelength (Chae ¶0030, 0146, “light may have a shorter wavelength band, … from the first color light L1 toward the third color light L3”); and
a luminous intensity of the first light emission stack (Chae 225, 223, 221) is lower than a luminous intensity of the second light emission stack (Chae 231, 233, 235)(Chae ¶0358 “light intensities, which may cause a difference in visibility … a red color … lower visibility than a green color”, ¶0472-0473);
a width of the first light emission stack is greater than each of a width of the second light emission stack (Chae fig 46, ¶0407, “the area of … 230 may be smaller than the area of … 220”, ¶0392, “a quadrangular shape”, for a quadrangular stack, having a greater area necessarily means a greater width, therefore 220 has an width greater than 230, and 230 has an width greater than 240).
Chae does not explicitly teach: opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view.
Chae-945, in the same field of endeavor of semiconductor device manufacturing, teaches: a third light emission stack (Chae-945 543, ¶0726) disposed over a second light emission stack (Chae-945 533, ¶0726)(Chae-945 fig 64-C, ¶0727); wherein
opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view (Chae-945, ¶0727, 0743, fig 59, 63, 64A-C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify an area of the third light emission stack of Chae, such that “opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view”, as taught by Chae-945, in order to leave a peripheral region of the second light emission stack uncovered by the third light emissions stack, thereby reducing and/or preventing light loss of the second emission stack (Chae-945 ¶0728-0729).
Regarding claim 18, Chae in view of Chae-945 teaches: The display apparatus of claim 15, further comprising an adhesive layer (Chae 60c, ¶0154, 0245) coupling the second light emission stack (Chae 231, 233, 235) and the third light emission stack (Chae 241, 243, 245)(Chae ¶0153, fig 2A).
Claims 6, 13, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al (US 20190189681 A1, hereafter Chae) in view of Chae et al (US 20190164945 A1, hereafter Chae-945), as applied to claims 1, 8, or 15 above, and further in view of Tsai et al (US 20210050475 A1, as disclosed in IDS dated 01/30/2026, hereafter Tsai).
Regarding claim 6, Chae in view of Chae-945 teaches: The display apparatus of claim 1, further comprising a cover layer (Chae 283, ¶0411) disposed over the first (Chae 220, 20), second (Chae 230, 30) and third (Chae 240, 40) light emitting devices (Chae fig 46, ¶0411, 0413, “polyimide”, under a broadest reasonable interpretation (BRI) of “cover layer”).
Chae in view of Chae-945 does not explicitly teach: wherein the cover layer has a thickness greater than or equal to 1μm.
Tsai, in the same field of endeavor of semiconductor device manufacturing, teaches: a cover layer (Tsai 440, ¶0050, fig 9, under a BRI of “cover layer”) has a thickness greater than or equal to 1μm (Tsai ¶0050, “440 may have a thickness of not less than 1 μm”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the thicknesses of the cover layer of Chae in view of Chae-945, such that “wherein the cover layer has a thickness greater than or equal to 1μm”, in order provide physical protection to the light emitting devices (Tsai ¶0050), and/or to provide sufficient electrical insulation (Chae ¶0411), thereby preventing physical damage during manufacturing and/or preventing electrical shorting.
Further, the adjustment of thickness of a cover layer is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a thickness is disclosed by Tsai, and therefore discovering the optimum or working range of “a thickness greater than or equal to 1μm " involves only routine skill in the art.
Regarding claim 13, Chae in view of Chae-945 teaches: The display apparatus of claim 8, further comprising a cover layer (Chae 283, ¶0411) disposed over the first (Chae 220, 20), second (Chae 230, 30) and third (Chae 240, 40) light emitting devices (Chae fig 46, ¶0411, 0413, “polyimide”, under a BRI of “cover layer”).
Chae in view of Chae-945 does not explicitly teach: wherein the cover layer has a thickness greater than or equal to 1μm.
Tsai, in the same field of endeavor of semiconductor device manufacturing, teaches: a cover layer (Tsai 440, ¶0050, fig 9, under a BRI of “cover layer”) has a thickness greater than or equal to 1μm (Tsai ¶0050, “440 may have a thickness of not less than 1 μm”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the thicknesses of the cover layer of Chae in view of Chae-945, such that “wherein the cover layer has a thickness greater than or equal to 1μm”, in order provide physical protection to the light emitting devices (Tsai ¶0050), and/or to provide sufficient electrical insulation (Chae ¶0411), thereby preventing physical damage during manufacturing and/or preventing electrical shorting.
Further, the adjustment of thickness of a cover layer is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general conditions of a thickness is disclosed by Tsai, and therefore discovering the optimum or working range of “a thickness greater than or equal to 1μm " involves only routine skill in the art.
Regarding claim 19, Chae in view of Chae-945 teaches: The display apparatus of claim 15, further comprising a cover layer (Chae 283, ¶0411) disposed over the first (Chae 220, 20) and second (Chae 230, 30) light emitting devices (Chae fig 46, ¶0411, 0413, “polyimide”, under a BRI of “cover layer”).
Chae in view of Chae-945 does not explicitly teach: wherein the cover layer has a thickness greater than or equal to 1μm.
Tsai, in the same field of endeavor of semiconductor device manufacturing, teaches: a cover layer (Tsai 440, ¶0050, fig 9, under a BRI of “cover layer”) has a thickness greater than or equal to 1μm (Tsai ¶0050, “440 may have a thickness of not less than 1 μm”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the thicknesses of the cover layer of Chae in view of Chae-945, such that “wherein the cover layer has a thickness greater than or equal to 1μm”, in order provide physical protection to the light emitting devices (Tsai ¶0050), and/or to provide sufficient electrical insulation (Chae ¶0411), thereby preventing physical damage during manufacturing and/or preventing electrical shorting.
Further, the adjustment of thickness of a cover layer is a matter of routine optimization. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (MPEP 2144.05). In the instant case, the general condition of a thickness is disclosed by Tsai, and therefore discovering the optimum or working range of “a thickness greater than or equal to 1μm " involves only routine skill in the art.
Regarding claim 20, Chae in view of Chae-845 and Tsai teaches: The display apparatus of claim 19, further comprising a connection layer (Chae 221n, 231n, ¶0316-0317) that is electrically connected to the first (Chae 220, 20) and second (Chae 230, 30) light emitting devices (Chae fig 46, ¶0339),
wherein the cover layer (Chae 283 as modified by Tsai 440) is disposed over the connection layer (Chae fig 46, ¶0412, 0415).
Claims 15-17 are ejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 20160372514 A1, hereafter Chang) in view of Chae et al (US 20190164945 A1, hereafter Chae-945).
Regarding claim 15, Chang teaches: A display apparatus (Chang 10, fig 3, 4, ¶0032-0035), comprising:
a circuit board (Chang 110, fig 3, 4, ¶0032, 0035, “110 comprises a plurality of pixel circuits T1, T2, T3”); and
a light source (Chang 100, fig 3, 4, ¶0032, 0035) connected to the circuit board (Chang fig 4, ¶0035), the light source including:
a first light emitting device (Chang 120, 101, 100R, ¶0032, 0034);
a second light emitting device (Chang 130, 102, 100G, ¶0032, 0034) disposed adjacent to the first light emitting device (Chang fig 4); and
a third light emitting device (Chang 140, 103, 100B, ¶0032, 0034) disposed adjacent to the second light emitting device (Chang fig 4), wherein:
the first light emitting device includes a first light emission stack (Chang 121, 122, 123, fig, 4, ¶0035, 0037) configured to generate a light having a first peak wavelength (Chang ¶0034, 0037, 0045, red light);
the second light emitting device includes a second light emission stack (Chang 131, 132, 133, fig, 4, ¶0035, 0037) configured to generate a light having a second peak wavelength (Chang ¶0034, 0037, 0045, green light) that is shorter than the first peak wavelength (Chang fig 7, ¶0045, green light having a short wavelength than red);
the third light emitting device includes a third light emission stack (Chang 141, 142, 143, fig, 4, ¶0035, 0037) configured to generate a light having a third peak wavelength (Chang ¶0034, 0037, 0045, blue light) that is shorter than the second peak wavelength (Chang fig 7, ¶0045, blue light having a short wavelength than green);
a luminous intensity of the first light emission stack is lower than a luminous intensity of the second light emission stack (Chang fig 2, ¶0014, 0030, 0040, 0045 “inferior luminous efficiency of the red sub-pixel 100R”);
a width of the first light emission stack is greater than a width of the second light emission stack (Chang fig 6, ¶0038, 0040, “AR≧AG≧AB”, ¶0054, “depicts as rectangles”, for a rectangular stack, having a greater area necessarily means a greater width, therefore 120 has a width greater than 130).
Chang does not explicitly teach: opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view.
Chae-945, in the same field of endeavor of semiconductor device manufacturing, teaches: a third light emission stack (Chae-945 543, ¶0726) disposed over a second light emission stack (Chae-945 533, ¶0726)(Chae-945 fig 64-C, ¶0727); wherein
opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view (Chae-945, ¶0727, 0743, fig 59, 63, 64A-C).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify an area of the third light emission stack of Chang, such that “opposite peripheral edges of the third light emission stack are disposed between corresponding opposite peripheral edges of the second light emission stack in plan view”, as taught by Chae-945, in order to leave a peripheral region of the second light emission stack uncovered by the third light emissions stack, thereby reducing and/or preventing light loss of the second emission stack (Chae-945 ¶0728-0729).
Regarding claim 16, Chang in view of Chae-945 teaches: The display apparatus of claim 15, wherein:
the first light emission stack (Chang 121, 122, 123) includes an arsenic (Chang ¶0037, “GaAs”) or phosphide-based semiconductor layer; and
the second (Chang 131, 132, 133) and third light emission stacks (Chang 141, 142, 143) include a nitride-based semiconductor layer (Chang ¶0037, “gallium nitride or indium gallium nitride (InGaN)”).
Regarding claim 17, Chang in view of Chae-945 teaches: The display apparatus of claim 15, wherein the first light emission stack (Chang 121, 122, 123) and the second light emission stack (Chang 131, 132, 133) are arranged in a lateral direction (Chang fig 4, 6).
Response to Arguments
Applicant’s arguments filed 06/12/2026, with respect to the specification has been fully considered and is persuasive. The objection to the specification has been withdrawn.
Applicant’s arguments filed 06/12/2026, with respect to claims 1, 7, 8, and 14-20 have been fully considered and are persuasive. The 35 USC § 112 rejections of claims 1, 7, 8, and 14-20 have been withdrawn.
Applicant’s arguments filed 06/12/2026, with respect to rejections made under 35 USC § 102 or 103 of claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Chae et al (US 20190164945 A1) teaches the amended limitations, as disclosed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
Prosecution Insights