DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to a Restriction Requirement mailed on 04/16/2026, the Applicant elected without traverse Group I (claims 1-18) and withdrew claims 19-20 of the non-elected Group II in a reply filed on 06/15/2026.
Currently, claims 1-18 are examined as below.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device Assemblies with Cross-Stack Structures
(Clean Version) Semiconductor Device Assemblies with Cross-Stack Structures
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 is indefinite, because the limitation “the first die” in lines 2-3 is not mentioned before. Only a first semiconductor die is recited in claim 11. There is insufficient antecedent basis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-11, 13-14 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0130797 A1 to Kang.
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Regarding independent claim 1, Kang in Figs. 6-7 teaches a semiconductor device assembly 14, 15 (Figs. 6-7 & ¶ 73, semiconductor package 14, 15), comprising:
an assembly substrate 100 (¶ 73, substrate 100) including an upper surface (Figs. 6-7);
a first and second die stack 300, 700, 200, 600 (Figs. 6-7, ¶ 73, a collective of second lower stack 300 and second upper stack 700 is the first die stack, and a collective of first lower stack 200 and first upper stack 600 is the second die tack) at the upper surface, each including multiple semiconductor dies 201-203, 601-604, 301-303, 701-704 (Figs. 6-7, ¶ 41, ¶ 44, ¶ 74-¶ 75, first lower semiconductor chips, 201-203, first upper semiconductor chips 601-604, second lower semiconductor chips 301-303 and second upper semiconductor chips 701-704) in electric communication with the assembly substrate 100 (¶ 30, ¶ 35, ¶ 40, ¶ 42, ¶ 45, the substrate 100 electrically connects to the stacks 200, 300 and the redistribution substrate 500, and the redistribution substrate 500 electrically connects to the first upper stack 600 and the second upper stack 700. In other words, the substrate 100 electrically connects to the stacks 200, 300, 600, 700);
a cross-stack substrate 500 (Figs. 6-7, ¶ 73, redistribution substrate 500) spaced from the upper surface and coupled to and extending between the first and second die stacks 300, 700, 200, 600, wherein the cross-stack substrate 500 is coupled between a first and second semiconductor die 701, 601, 303, 203 (Figs. 6-7) of the first and second die stacks 300, 700, 200, 600, respectively; and
a passive semiconductor component 750 (Figs. 6-7, ¶ 45, second upper connector 750, and a connector is the same passive semiconductor component (i.e., connector) as the Applicant purported in paragraph 31 in the specification of the present application) carried by the cross-stack substrate 500 and in electric communication with the assembly substrate 100 (¶ 40, ¶ 45, the second upper connector 750 electrically connects to the substrate 500, which electrically connects to the substrate 100), wherein the passive semiconductor component 750 is further in electric communication with the first semiconductor die 701 of the first die stack 700 exclusively via the assembly substrate 100 (Figs. 6-7, ¶ 40, the connector 750 electrically connects to the die 701 has an exclusive connection to the substrate 100 through the connector 550).
Regarding claim 2, Kang in Figs. 6-7 further teaches the passive semiconductor component 750 is further in electric communication with the second semiconductor die 303 of the first die stack 300, 700 (¶ 35, ¶ 40, ¶ 45, the stack 300 including the chip 303 electrically connects to the substrate 100, which electrically connects to the connector 550, and the connector 550 electrically connects to the connector 750 through the substrate 500).
Regarding claim 3, Kang in Figs. 6-7 the passive semiconductor component 750 is further in electric communication with the first semiconductor die 601 of the second die stack 200, 600 (Figs. 6-7, ¶ 48, the component 750 electrically connects to the die 601 via the redistribution pattern 530).
Regarding claim 4, Kang in Fig. 6 further teaches the multiple semiconductor dies 301-303, 701-704 of the first die stack 300, 700 are shingled toward the second die stack 200, 600.
Regarding claim 5, Kang in Fig. 6 further teaches at least some of the multiple semiconductor dies 201-203 of the second die stack 200, 600 are shingled toward the first die stack 300, 700.
Regarding claim 6, Kang in Fig. 7 further teaches the multiple semiconductor dies 301-303, 701-704 of the first die stack 300, 700 are shingled along a first direction (Fig. 7), and the second die stack 200, 600 is separated from the first die stack 300, 700 along a first distance perpendicular to the first direction (Fig. 7).
Regarding claim 8, Kang in Figs. 6-7 further teaches the passive semiconductor component 750 (Figs. 6-7, an upper second upper connector 750) is in electric communication with the assembly substrate 100 via (i) a first interconnection 750 (Figs. 6-7, ¶ 45, a lower second upper connector 750) between the passive semiconductor component 750 and the cross-stack substrate 500, (ii) the cross-stack substrate 500 (Figs. 6-7, ¶ 45), and (iii) a second interconnection 550 (Figs. 6-7, ¶ 40, redistribution connector 550) between the cross-stack substrate 500 and the assembly substrate 100.
Regarding claim 9, Kang in Figs. 6-7 further teaches a controller 900 (¶ 33, controller 900) at the upper surface of the assembly substrate 100 (Figs. 6-7), wherein the controller 900 is in electric communication with the assembly substrate 100 (¶ 33).
Regarding claim 10, Kang in Figs. 6-7 further teaches the controller 900 is further in electric communication with the passive semiconductor component 750 exclusively via the assembly substrate 100 (Figs. 6-7, ¶ 33, ¶ 40).
Regarding independent claim 11, Kang in Figs. 6-7 teaches a semiconductor device assembly 14, 15 (Figs. 6-7 & ¶ 73, semiconductor package 14, 15), comprising:
an assembly substrate 100 (¶ 73, substrate 100) including an upper surface (Figs. 6-7);
a first and second die stack 300, 700, 200, 600 (Figs. 6-7, ¶ 73, a collective of second lower stack 300 and second upper stack 700 is the first die stack, and a collective of first lower stack 200 and first upper stack 600 is the second die tack) at the upper surface, each including multiple semiconductor dies 201-203, 601-604, 301-303, 701-704 (Figs. 6-7, ¶ 41, ¶ 44, ¶ 74-¶ 75, first lower semiconductor chips, 201-203, first upper semiconductor chips 601-604, second lower semiconductor chips 301-303 and second upper semiconductor chips 701-704);
a cross-stack substrate 500 (Figs. 6-7, ¶ 73, redistribution substrate 500) spaced from the upper surface and coupled to and extending between the first and second die stacks 300, 700, 200, 600, wherein the cross-stack substrate 500 is coupled between a first and second semiconductor die 701, 601, 303, 203 (Figs. 6-7) of the first and second die stacks 200, 300, 600, 700, respectively, and wherein the cross-stack substrate 500 includes a top and bottom surface (Figs. 6-7);
a top passive semiconductor component 750 (Figs. 6-7, ¶ 45, second upper connector 750, and a connector is the same passive semiconductor component (i.e., connector) as the Applicant purported in paragraph 31 in the specification of the present application) carried by the top surface of the cross-stack substrate 500; and
a bottom passive semiconductor component 250 (Figs. 6-7, ¶ 30, first lower connector 250, and a connector is the same passive semiconductor component (i.e., connector) as the Applicant purported in paragraph 31 in the specification of the present application) carried by the bottom surface of the cross-stack substrate 500.
Regarding claim 13, Kang in Figs. 6-7 further teaches the top passive semiconductor component 750 is in electric communication with the assembly substrate 100 (Figs. 6-7, ¶ 40, ¶ 45), wherein the first die 701 (Figs. 6-7) of the first die stack 300, 700 is in electric communication with the assembly substrate 100 (Figs. 6-7, ¶ 40, ¶ 44-¶ 45), and wherein the first die 701 is in electric communication with the top passive semiconductor component 750 exclusively via the assembly substrate 100 (Figs. 6-7, ¶ 40, the connector 750 electrically connects to the die 701 has an exclusive connection to the substrate 100 through the connector 550).
Regarding claim 14, Kang in Figs. 6-7 further teaches the top passive semiconductor component 750 is in electric communication with the cross-stack substrate 500 via a wire bond interconnection 750 (¶ 45, second upper connector 750 is a bonding wire).
Regarding claim 17, Kang in Figs. 6-7 further teaches the top passive semiconductor component 750 is a first top passive semiconductor component 750 (Figs. 6-7, one of the multiple connectors 750) and the assembly 14, 15 further comprises a second top passive semiconductor component 750 (Figs. 6-7, the other one of the multiple connectors 750) at the top surface of the cross-stack substrate 500.
Regarding claim 18, Kang in Figs. 6-7 further teaches the bottom passive semiconductor component 250 is a first bottom passive semiconductor component 250 (Figs. 6-7, one of the multiple connectors 250) and the assembly 14, 15 further comprises a second bottom passive semiconductor component 250 (Figs. 6-7, the other one of the multiple connectors 250) at the bottom surface of the cross-stack substrate 500.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of US 2013/0221470 A1 to Kinsman et al. (“Kinsman”).
Regarding claim 15, Kang in Figs. 6-7 teaches the top passive semiconductor component 750 (¶ 45, bonding wire 750) is in electric communication with the cross-stack substrate 500.
Kang does not explicitly disclose the bonding wire 750 is in electrical communication with the substrate 500 via a solder bond interconnection.
Kinsman recognizes a need for providing a compact stacked-chip package (¶ 4-¶ 5). Kinsman satisfies the need by providing a bonding wire 108 (Fig. 3, ¶ 24, bond wire 108) in electrical communication with a substrate 100 (Fig. 3, ¶ 24, substate 100) via a solder bond interconnection (Fig. 3, ¶ 32, ¶ 44, the wire 108 is soldered to the substrate 100).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the passive component and the substrate taught by Kang with the solder taught by Kinsman, so as to provide a compact stacked-chip package (Kinsman: ¶ 4-¶ 5).
Regarding claim 16, Kang in Figs. 6-7 teaches the bottom passive semiconductor component 250 (¶ 30, bonding wire 250) is in electric communication with the cross-stack substrate 500 (Figs. 6-7, ¶ 30, ¶ 40, bonding wire 250 electrically connects to the substrate 100, and the substrate 100 electrically connects to the cross-stack substrate 500. In other words, the bonding wire 250 electrically connects to the substrate 500).
Kang does not explicitly disclose the bonding wire 250 is in electrical communication with the substrate 500 via a hybrid bond interconnection.
Kinsman recognizes a need for providing a compact stacked-chip package (¶ 4-¶ 5). Kinsman satisfies the need by providing a bonding wire 108 (Fig. 3, ¶ 24, bond wire 108) in electrical communication with a substrate 100 (Fig. 3, ¶ 24, substate 100) via a hybrid bond interconnection (Fig. 3, ¶ 32, ¶ 44, the wire 108 is soldered to the substrate 100, which is a hybrid bond interconnection including wire bonding and solder bonding).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the passive component and the substrate taught by Kang with the solder taught by Kinsman, so as to provide a compact stacked-chip package (Kinsman: ¶ 4-¶ 5).
The combination of Kang and Kinsman discloses the bonding wire 250 (Kang) electrically connects to the substrate 100 (Kang) via a hybrid bond interconnection (Kinsman), and the substrate 100 electrically connects to the substrate 500 (Kang). In other words, Kang’s wire 250 electrically connects to the substrate 500 via the hybrid bond interconnection.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 7 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 7 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, the assembly further comprises a second cross-stack substrate spaced from the upper surface of the assembly substrate and from the first cross-stack substrate and extending between the first and second die stacks, wherein the second cross-stack substrate is coupled between a third and fourth semiconductor die of the first and second die stacks, respectively.
Claim 12 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, wherein the first semiconductor die of the first and second die stacks is one of eight semiconductor dies of the lower die sub-stacks, respectively, and wherein the second semiconductor die of the first and second die stacks is one of eight semiconductor dies of the upper die sub-stacks.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0111152 A1 to Park et al. relates to a semiconductor package including a base substrate, a printed circuit board disposed on the base substrate, a first chip stack disposed on the base substrate on one side of the printed circuit board, a second chip stack disposed on the first chip stack, a third chip stack disposed on the base substrate on the other side of the printed circuit board, and a fourth chip stack disposed on the third chip stack, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board.
US 2018/0122771 A1 to Park relates to a semiconductor package including a first chip stack including first chips which are stacked on a package substrate and a second chip stack including second chips which are stacked on the package substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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