DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-8, 10-15, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yen et al. (US publication 2022/0359363 A1), hereinafter referred to as Yen363.
Regarding claim 1, Yen363 teaches a package structure (fig. 2 and related text), comprising: an interposer including a first die (210/220, ([0027 and 0048-0049]) sandwiched between a first redistribution layer (RDL) structure (514, [0044]) and a second RDL structure (524, [0045]), wherein the first die comprises: a device layer (210/220 has device layer) disposed on a substrate (100, [0025]); an inductor device disposed on the device layer ([0049]); an internal RDL structure (410/420/422, [0031-0033]) disposed on the inductor device (fig. 2); a plurality of conductive connectors (40, [0045]) disposed on the internal RDL structure (fig. 2); and an inductor contact (522, [0041]) disposed aside the inductor device and electrically connecting the internal RDL structure and the inductor device (fig. 2).
Regarding claim 2, Yen363 teaches wherein the internal RDL structure has a conductive feature (410, [0031]) across the inductor device (fig. 2).
Regarding claim 3, Yen363 teaches wherein a conductive feature (410, [0031]) of the internal RDL structure laterally surrounds the inductor device in a circular arrangement, so that the conductive feature of the internal RDL structure is not disposed directly over the inductor device (fig. 2).
Regarding claim 4, Yen363 teaches wherein the plurality of conductive connectors laterally surround the inductor device in a circular arrangement from a plan view of the internal RDL structure (fig. 2).
Regarding claim 5, Yen363 teaches wherein the plurality of conductive connectors are disposed over the inductor device in an array arrangement from a plan view of the internal RDL structure (fig. 2).
Regarding claim 6, Yen363 teaches wherein the first die further comprises: a plurality of substrate-through vias (TSVs) (410, [0031]) penetrating through the substrate to electrically connect the device layer and the second RDL structure (fig. 2); and a planarization layer encapsulating the substrate, the device layer, the inductor device ([0026]), and the inductor contact to contact a bottom surface of the internal RDL structure (fig. 2).
Regarding claim 7, Yen363 teaches wherein the internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors, and the number of the plurality of conductive connectors is greater than the number of the inductor contact (fig. 2).
Regarding claim 8, Yen363 teaches wherein the interposer further comprises: a second die (220 on left) arranged parallel to the first die (220 on right); a plurality of insulator-through vias (TIVs) (410, [0031]) laterally surrounding the first die and the second die; and a first encapsulant laterally encapsulating the first die, the second die, and the plurality of TIVs (fig. 2).
Regarding claim 10, Yen363 teaches further comprising: one or more package components (20, [0024]) disposed over the first RDL structure; a second encapsulant (760, [0042]) laterally encapsulating the one or more package components; a plurality of conductive terminals (30, [0024]) disposed on the second RDL structure; and a package substrate bonded to the interposer through the plurality of conductive terminals (fig. 2).
Regarding claim 11, Yen363 teaches a package structure (fig. 2 and related text), comprising: an interposer including a first package component (10/20, [0024]) sandwiched between a first RDL structure (524, [0045]) and a second RDL structure (514, [0044]), wherein the first package component comprises: a bottom die (710, [0042]); an inductor device (20 on left, [0048-0049], an active device die (210, [0027]), and a passive device die (20 on right, [0048-0049] arranged side by side on the bottom die (fig. 2); an internal RDL structure (420, [0031-0033]) disposed on the inductor device, the active device die, and the passive device die (fig. 2); and a plurality of conductive connectors (40, [0045]) disposed on the internal RDL structure to electrically connect the internal RDL structure and the first RDL structure (fig. 2)
Regarding claim 12, Yen363 teaches wherein the first package component further comprises: an inductor contact (522, [0041]) disposed aside the inductor device and vertically sandwiched between the bottom die and the internal RDL structure, wherein the internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors (fig. 2).
Regarding claim 13, Yen363 teaches wherein the bottom die comprises: a substrate (100, [0025]); a device layer (210/220 has device layer) disposed on the substrate; a plurality of substrate-through vias (TSVs) (410, [0031-0033]) penetrating through the substrate to electrically connect the device layer and the second RDL structure (fig. 2).
Regarding claim 14, Yen363 teaches wherein the interposer further comprises: a plurality of insulator-through vias (TIVs) (410, [0031]) laterally surrounding the first package component; and a first encapsulant laterally encapsulating the first package component and the plurality of TIVs (fig. 2).
Regarding claim 15, Yen363 teaches further comprising: one or more second package (20, [0024]) components disposed over the first RDL structure; a second encapsulant (760, [0042]) laterally encapsulating the one or more second package components; a plurality of conductive terminals (30, [0024]) disposed on the second RDL structure; and a package substrate bonded to the interposer through the plurality of conductive terminals (fig. 2).
Regarding claim 17, Yen363 teaches a method of forming a package structure (a method of making of fig. 2 and related text), comprising: forming a first die (210/220, ([0027 and 0048-0049]) on a first RDL structure (514, [0044]); forming a second RDL structure (524, [0045]) on the first die to form an interposer (fig. 2); and forming a plurality of conductive terminals (30, [0024]) on the second RDL structure, wherein the first die comprises: a device layer (210/220 has device layer) formed on a substrate (100, [0025]); an inductor device formed on the device layer ([0049]); an internal RDL structure (420, [0031-0033]) formed on the inductor device; a plurality of conductive connectors (40, [0045]) formed on the internal RDL structure; and an inductor contact (522, [0041]) formed aside the inductor device and electrically connecting the internal RDL structure and the inductor device (fig. 2), wherein the internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors (fig. 2).
Regarding claim 18, Yen363 teaches wherein the forming the interposer further comprises: arranging a second die (220 on left) parallel to the first die (220 on right); forming a plurality of insulator-through vias (TIVs) (410, [0031]) to laterally surround the first die and the second die; and forming a first encapsulant to laterally encapsulate the first die, the second die, and the plurality of TIVs (fig. 2).
Regarding claim 20, Yen363 teaches further comprising: forming one or more package components (20, [0024]) over the first RDL structure; and forming a second encapsulant (760, [0042]) to laterally encapsulate the one or more package components (fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yen363, as applied to claim 1 or 17 above, and further in view of Kawabata et al. (US publication 2006/0131740 A1), hereinafter referred to as Kawabata.
Regarding claim 9, Yen363 discloses all the limitations of claim 1 as discussed above on which this claim depends.
Yen363 does not explicitly teach wherein the interposer further comprises: a second die vertically stacked over the first die to form a die stack structure; a plurality of insulator-through vias (TIVs) laterally surrounding the die stack structure; and a first encapsulant laterally encapsulating the die stack structure and the plurality of TIVs.
Kawabata teaches wherein the interposer further comprises: a second die vertically stacked over the first die to form a die stack structure ([0089-0092], fig. 9); a plurality of insulator-through vias (TIVs) (7, [0064]) laterally surrounding the die stack structure; and a first encapsulant (3, [0064]) laterally encapsulating the die stack structure and the plurality of TIVs (fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yen363 with that of Kawabata so that wherein the interposer further comprises: a second die vertically stacked over the first die to form a die stack structure; a plurality of insulator-through vias (TIVs) laterally surrounding the die stack structure; and a first encapsulant laterally encapsulating the die stack structure and the plurality of TIVs for forming multi-level semiconductor modules by stacking and uniting a plurality of electronic components for size reduction and performance improvement ([0005]).
Regarding claim 19, Yen363 discloses all the limitations of claim 17 as discussed above on which this claim depends.
Yen363 does not explicitly teach wherein the forming the interposer further comprises: stacking a second die vertically over the first die to form a die stack structure; forming a plurality of insulator-through vias (TIVs) to laterally surround the die stack structure; and forming a first encapsulant to laterally encapsulate the die stack structure and the plurality of TIVs.
Kawabata teaches wherein the forming the interposer further comprises: stacking a second die vertically over the first die to form a die stack structure ([0089-0092], fig. 9); forming a plurality of insulator-through vias (TIVs) (7, [0064]) to laterally surround the die stack structure; and forming a first encapsulant (3, [0064]) to laterally encapsulate the die stack structure and the plurality of TIVs (fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yen363 with that of Kawabata so that wherein the forming the interposer further comprises: stacking a second die vertically over the first die to form a die stack structure; forming a plurality of insulator-through vias (TIVs) to laterally surround the die stack structure; and forming a first encapsulant to laterally encapsulate the die stack structure and the plurality of TIVs for forming multi-level semiconductor modules by stacking and uniting a plurality of electronic components for size reduction and performance improvement ([0005]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yen363, as applied to claim 11 above, and further in view of Ganesan et al. (US publication 2022/0293327 A1), hereinafter referred to as Ganesan.
Regarding claim 16, Yen363 discloses all the limitations of claim 11 as discussed above on which this claim depends.
Yen363 does not explicitly teach wherein the inductor device comprises: a coil structure and a magnetic material wrapping the coil structure.
Ganesan teaches wherein the inductor device comprises: a coil structure (160) and a magnetic material (170) wrapping the coil structure ([0046-0049], fig. 17-18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yen363 with that of Ganesan so that wherein the inductor device comprises: a coil structure and a magnetic material wrapping the coil structure for the integration of magnetic materials into coreless electronic substrates to form inductors to produce ever faster and smaller integrated circuit devices ([0001-0002]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
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