Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, pages 1-2, filed on 08/14/2026, with respect to Double Patenting Rejection have been fully considered and are persuasive. Therefore, the rejection of Double Patenting will be held in abeyance until the final content of an allowable set of claims has been determined.
Applicant's arguments filed on 08/14/2026 have been fully considered but they are not persuasive.
The Applicant argues that in regard to claims 1 and 13 that the Haeberlen prior art, does not teach the limitation of “vertical power transistor.”
In response to this argument, the Examiner directs the applicant’s attention to Haeberlen prior art, which teaches the recited limitation as follows:
Haeberlen teaches a vertical power transistor (note: gate electrode 11, gate dielectric 12, vertical channel at the interface between the gate dielectric 12 and p- doped region 50, source region 80, source electrode 21 and 60, drain region 41, and drain electrode 42 necessary forms a vertical power transistor. Note: electrode 21 allows the source electrode 60 to electrically connect to the field plate electrode 16 through p-type third conductive region 25 and drift region 40 and results ultra-low drift layer resistance and high breakdown voltage) formed in the semiconductor substrate (see Haeberlen, Fig.13 as shown below).
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the Haeberlen prior art reference does meet all the limitation in claims 1 and 13.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10, 12-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haeberlen et al. (U.S. 2010/0078707 A1, hereinafter refer to Haeberlen).
Regarding Claim 1: Haeberlen discloses a semiconductor device (see Haeberlen, Fig.13 as shown below and ¶ [0001]), comprising:
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a semiconductor substrate having a first main surface (see Haeberlen, Fig.13 as shown above);
a vertical power transistor (note: gate electrode 11, gate dielectric 12, vertical channel at the interface between the gate dielectric 12 and p- doped region 50, source region 80, source electrode 21 and 60, drain region 41, and drain electrode 42 necessary forms a vertical power transistor. Note: electrode 21 allows the source electrode 60 to electrically connect to the field plate electrode 16 through p-type third conductive region 25 and drift region 40 and results ultra-low drift layer resistance and high breakdown voltage) formed in the semiconductor substrate (see Haeberlen, Fig.13 as shown above) and comprising:
a source region (80) having a first conductivity type and formed in the semiconductor substrate (see Haeberlen, Fig.13 as shown above and ¶ [0044]);
a body region (50) having a second conductivity type opposite the first conductivity type and formed in the semiconductor substrate below the source region (80) (see Haeberlen, Fig.13 as shown above and ¶ [0044]);
a contact opening (20) extending from the first surface through the source region (80) and at least into the body region (50), the contact opening (20) forming at least one sidewall in the semiconductor substrate, the at least one sidewall comprising a first portion extending along the source region (80) and a second portion extending along the body region (50) (see Haeberlen, Fig.13 as shown above);
an electrically insulative spacer (22) partially covering the at least one sidewall, wherein the electrically insulative spacer (22) covers the entire second portion of the at least one sidewall and leaves at least a portion of the first portion of the at least one sidewall uncovered (see Haeberlen, Fig.13 as shown above);
a body contact region (25) having the second conductivity type and formed in the semiconductor substrate adjacent a bottom of the contact opening (20) (see Haeberlen, Fig.13 as shown above and ¶ [0086]); and
a contact plug (21 and 60) in the contact opening (20), the contact plug (21/60) being electrically connected with the source region (80) via the uncovered portion of the first portion of the at least one sidewall, and the contact plug (21/60) being electrically connected with the body contact region (25) (see Haeberlen, Fig.13 as shown above and ¶ [0099]- ¶ [0101]).
Regarding Claim 2: Haeberlen discloses a semiconductor device as set forth in claim 1 as above. Haeberlen further teaches wherein the vertical power transistor further comprises: a drift region (40) having the first conductivity type and formed in the semiconductor substrate below the body region (50) (see Haeberlen, Fig.13 as shown above);
wherein the contact opening (20) extends from the first surface through the source region (80) and through the body region (50) into the drift region (40), and wherein the body contact region (25) is formed in the drift region (40) (see Haeberlen, Fig.13 as shown above).
Regarding Claim 3: Haeberlen discloses a semiconductor device as set forth in claim 2 as above. Haeberlen further teaches wherein the body region (50) and the body contact region (25) are separated from each other by a portion of the drift region (40) (see Haeberlen, Fig.13 as shown above).
Regarding Claim 4: Haeberlen discloses a semiconductor device as set forth in claim 3 as above. Haeberlen further teaches wherein the at least one sidewall further comprises a third portion extending along the drift region (40), and wherein the third portion of the at least one sidewall is covered by the electrically insulative spacer (22) (see Haeberlen, Fig.13 as shown above).
Regarding Claim 5: Haeberlen discloses a semiconductor device as set forth in claim 4 as above. Haeberlen further teaches wherein the vertical power transistor further comprises: a trench (10) extending from the first main surface into the semiconductor substrate (see Haeberlen, Fig.13 as shown above); and
a gate electrode (11) in the trench (10) and insulated from the semiconductor substrate (see Haeberlen, Fig.13 as shown above);
wherein the source region (80), the body region (50), and the drift region (40) are formed adjacent the trench (10) such that the source region (80) and the body region (50) are located between the contact opening (20) and the trench (10) (see Haeberlen, Fig.13 as shown above).
Regarding Claim 6: Haeberlen discloses a semiconductor device as set forth in claim 5 as above. Haeberlen further teaches wherein the vertical power transistor further comprises: a field plate (16) in the trench (10) below the gate electrode (11), wherein the field plate (16) is electrically insulated from the gate electrode (11) (see Haeberlen, Fig.13 as shown above).
Regarding Claim 7: Haeberlen discloses a semiconductor device as set forth in claim 2 as above. Haeberlen further teaches wherein the vertical power transistor further comprises: a drain region (40) having the first conductivity type and formed at a second main surface of the semiconductor substrate opposite the first main surface (see Haeberlen, Fig.13 as shown above and ¶ [0044]),
wherein the drain region (41) is doped more heavily than the drift region (41) (see Haeberlen, Fig.13 as shown above and ¶ [0052]).
Regarding Claim 10: Haeberlen discloses a semiconductor device as set forth in claim 1 as above. Haeberlen further teaches wherein an interlayer dielectric (70) on the first main surface of the semiconductor substrate (see Haeberlen, Fig.13 as shown above),
wherein the contact opening (20) extends through the interlayer dielectric (20) and into the semiconductor substrate (see Haeberlen, Fig.13 as shown above), and
wherein a width of the contact opening (20) is larger in the interlayer dielectric (70) than in the semiconductor substrate (see Haeberlen, Fig.13 as shown above).
Regarding Claim 12: Haeberlen discloses a semiconductor device as set forth in claim 1 as above. Haeberlen further teaches wherein the electrically insulative spacer (22) comprises oxide, nitride, carbon or tetraethoxysilane (see Haeberlen, Fig.13 as shown above and ¶ [0055]).
Regarding Claim 13: Haeberlen discloses a semiconductor device (see Haeberlen, Fig.13 as shown above and ¶ [0001]), comprising:
a semiconductor substrate having a first main surface (see Haeberlen, Fig.13 as shown above);
a vertical power transistor (note: gate electrode 11, gate dielectric 12, vertical channel at the interface between the gate dielectric 12 and p- doped region 50, source region 80, source electrode 21 and 60, drain region 41, and drain electrode 42 necessary forms a vertical power transistor. Note: electrode 21 allows the source electrode 60 to electrically connect to the field plate electrode 16 through p-type third conductive region 25 and drift region 40 and results ultra-low drift layer resistance and high breakdown voltage) formed in the semiconductor substrate (see Haeberlen, Fig.13 as shown above) and comprising:
a source region (80) having a first conductivity type and formed in the semiconductor substrate (see Haeberlen, Fig.13 as shown above and ¶ [0044]);
a body region (50) having a second conductivity type opposite the first conductivity type and formed in the semiconductor substrate below the source region (80) (see Haeberlen, Fig.13 as shown above and ¶ [0044]);
a drift region (40) having the first conductivity type and formed in the semiconductor substrate below the body region (50) (see Haeberlen, Fig.13 as shown above);
a contact opening (20) extending from the first surface through the source region (80) and through the body region (50) into the drift region (40), the contact opening (20) forming at least one sidewall in the semiconductor substrate (see Haeberlen, Fig.13 as shown above);
an electrically insulative spacer (22) partially covering the at least one sidewall (see Haeberlen, Fig.13 as shown above);
a body contact region (25) having the second conductivity type and formed in the drift region (40) adjacent a bottom of the contact opening (20), wherein the body region (50) and the body contact region (25) are separated from each other by a portion of the drift region (40) (see Haeberlen, Fig.13 as shown above and ¶ [0086]); and
a contact plug (21 and 60) in the contact opening (20) (see Haeberlen, Fig.13 as shown above and ¶ [0099]- ¶ [0101]).
Regarding Claim 14: Haeberlen discloses a semiconductor device as set forth in claim 13 as above. Haeberlen further teaches wherein the vertical power transistor further comprises: a trench (10) extending from the first main surface into the semiconductor substrate (see Haeberlen, Fig.13 as shown above); and
a gate electrode (11) in the trench (10) and insulated from the semiconductor substrate (see Haeberlen, Fig.13 as shown above);
wherein the source region (80), the body region (50), and the drift region (40) are formed adjacent the trench (10) such that the source region (80) and the body region (50) are located between the contact opening (20) and the trench (10) (see Haeberlen, Fig.13 as shown above).
Regarding Claim 15: Haeberlen discloses a semiconductor device as set forth in claim 14 as above. Haeberlen further teaches wherein the vertical power transistor further comprises: a field plate (16) in the trench (10) below the gate electrode (11) (see Haeberlen, Fig.13 as shown above),
wherein the field plate (16) is electrically insulated from the gate electrode (11) (see Haeberlen, Fig.13 as shown above).
Regarding Claim 16: Haeberlen discloses a semiconductor device as set forth in claim 13 as above. Haeberlen further teaches wherein the vertical power transistor further comprises: a drain region (41) having the first conductivity type and formed at a second main surface of the semiconductor substrate opposite the first main surface (see Haeberlen, Fig.13 as shown above and ¶ [0052]),
wherein the drain region (41) is doped more heavily than the drift region (see Haeberlen, Fig.13 as shown above and ¶ [0052]).
Regarding Claim 17: Haeberlen discloses a semiconductor device as set forth in claim 13 as above. Haeberlen further teaches wherein an interlayer dielectric (70) on the first main surface of the semiconductor substrate (see Haeberlen, Fig.13 as shown above),
wherein the contact opening (20) extends through the interlayer dielectric (70) and into the semiconductor substrate (see Haeberlen, Fig.13 as shown above), and
wherein a width of the contact opening (20) is larger in the interlayer dielectric (70) than in the semiconductor substrate (see Haeberlen, Fig.13 as shown above).
Regarding Claim 19: Haeberlen discloses a semiconductor device as set forth in claim 13 as above. Haeberlen further teaches wherein the electrically insulative spacer (22) comprises oxide, nitride, carbon or tetraethoxysilane (see Haeberlen, Fig.13 as shown above and ¶ [0055]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8- 9 are rejected under 35 U.S.C. 103 as being unpatentable over Haeberlen et al. (U.S. 2010/0078707 A1, hereinafter refer to Haeberlen).
Regarding Claims 8 and 9: Haeberlen discloses a semiconductor device as applied to claim 1 above. First embodiment Fig.13 of Haeberlen’s is silent upon explicitly disclosing wherein the contact opening terminates within the body region such that the body contact plug is separated from the drift region by a section of the body region (as claimed in claim 8);
wherein the contact opening terminates within the body region, and wherein the body contact region is formed in the body region (as claimed in claim 9).
However, second embodiment of Haeberlen’s teaches wherein the contact opening (20) terminates within the body region (50) such that the body contact plug (21/60) is separated from the drift region (40) by a section of the body region (50) (see Haeberlen, Figs.14-15 as shown below and ¶ [0103]- ¶ [0107]) (as claimed in claim 8);
wherein the contact opening (20) terminates within the body region (50), and wherein the body contact region (25) is formed in the body region (50) (see Haeberlen, Figs.14-15 as shown below and ¶ [0103]- ¶ [0107]) (as claimed in claim 9).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of first embodiment of Haeberlen’s and second embodiment of Haeberlen’s to enable the first embodiment of Haeberlen’s contact opening to terminate within the body region such that the body contact plug is separated from the drift region by a section of the body region and the body contact region to be formed in the body region as taught by second embodiment of Haeberlen’s in order to balance the trade-off between Ron and electric losses in reversed mode.
Claim(s) 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Haeberlen et al. (U.S. 2010/0078707 A1, hereinafter refer to Haeberlen) as applied to claims 1 and 13 above, and further in view of Tihanyi (U.S. 2002/0000566 A1, hereinafter refer to Tihanyi).
Regarding Claim 11: Haeberlen discloses a semiconductor device as applied to claim 1 above. Haeberlen is silent upon explicitly disclosing wherein an interlayer dielectric on the first main surface of the semiconductor substrate,
wherein the contact opening extends through the interlayer dielectric and into the semiconductor substrate, and
wherein the electrically insulative spacer extends along sidewalls of the interlayer dielectric formed by the contact opening.
For support see Tihanyi, which teaches wherein an interlayer dielectric (70 and a portion of insulating layer 72) on the first main surface of the semiconductor substrate (see Tihanyi, Fig.2 as shown below and ¶ [0006]),
wherein the contact opening extends through the interlayer dielectric (70 and the portion of insulating layer 72) and into the semiconductor substrate (see Tihanyi, Fig.2 as shown below and ¶ [0006]), and
wherein the electrically insulative spacer (74 and the portion of insulating layer 72, note, the integral insulating layer 72 is equivalent to the claimed limitation of separable “electrical insulative spacer” and “interlayer dielectric” because mere duplication of layer has no patentable significance unless a new and unexpected result is produced) extends along sidewalls of the interlayer dielectric (a portion of insulating layer 72) formed by the contact opening (see Tihanyi, Fig.2 as shown below and ¶ [0006]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Haeberlen and Tihanyi to enable the Haeberlen electrically insulative spacer to extend along sidewalls of the interlayer dielectric formed by the contact opening as taught by Tihanyi in order to obtain a semiconductor switching element in which a transistor which can be controlled by a field effect and a Schottky diode are integrated in a semiconductor body.
Regarding Claim 18: Haeberlen discloses a semiconductor device as applied to claim 13 above. Haeberlen is silent upon explicitly disclosing wherein an interlayer dielectric on the first main surface of the semiconductor substrate,
wherein the contact opening extends through the interlayer dielectric and into the semiconductor substrate, and
wherein the electrically insulative spacer extends along sidewalls of the interlayer dielectric formed by the contact opening.
For support see Tihanyi, which teaches wherein an interlayer dielectric (70 and a portion of insulating layer 72) on the first main surface of the semiconductor substrate (see Tihanyi, Fig.2 as shown above and ¶ [0006]),
wherein the contact opening extends through the interlayer dielectric (70 and the portion of insulating layer 72) and into the semiconductor substrate (see Tihanyi, Fig.2 as shown above and ¶ [0006]), and
wherein the electrically insulative spacer (74 and the portion of insulating layer 72, note, the integral insulating layer 72 is equivalent to the claimed limitation of separable “electrical insulative spacer” and “interlayer dielectric” because mere duplication of layer has no patentable significance unless a new and unexpected result is produced) extends along sidewalls of the interlayer dielectric (a portion of insulating layer 72) formed by the contact opening (see Tihanyi, Fig.2 as shown above and ¶ [0006]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Haeberlen and Tihanyi to enable the Haeberlen electrically insulative spacer to extend along sidewalls of the interlayer dielectric formed by the contact opening as taught by Tihanyi in order to obtain a semiconductor switching element in which a transistor which can be controlled by a field effect and a Schottky diode are integrated in a semiconductor body.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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