DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/443,355, application filed on 02/16/2024. Claims 1-11 are currently pending in this application.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 02/16/2024 and 01/08/2025, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1-2 and 7 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Afshar et al. (US PG Pub No. 2013/0162292).
7. With respect to independent claim 1, Afshar teaches:
A programmable logic circuit (see reconfigurable circuit, para 12; programmable integrated circuit, para 20; see programmable logic block, para 31; see enabling/disabling inverter for logic circuit, para 33-34), comprising:
a basic logic cell for configuring a plurality of nodes of a gate-level netlist (see logic blocks with plurality of nodes, para 9; logic nodes based on gate-level netlist, para 32; see netlist, at gate-level and nodes of logic cell, para 43-45),
wherein the basic logic cell is a programmable circuit (each cell includes a selectably coupled inverter, para 12; each cell is configurable or programmable, para 14) configured by adding one or more programmable NOT circuits to a basic logic operation element (see each cell includes a conditional inversion/NOT which is configurable/programmable, para 14; see programmable conditional inversion, Abstract, para 31, 44) and made programmable to switch inputs and outputs of the basic logic cell (using crossbar switch to route any input to any output, para 62) depending on connection relationships of nodes in the gate-level netlist (see using crossbar switch to route inputs to outputs based on netlist and graph defining connections for AIG’s, para 62-69).
8. With respect to independent claim 7, Afshar teaches:
A method for configuring a programmable logic circuit (see reconfigurable circuit, para 12; programmable integrated circuit, para 20; see programmable logic block, para 31; see enabling/disabling inverter for logic circuit, para 33-34),
wherein nodes constituting a gate-level netlist are assigned to a programmable logic cell (see logic blocks with plurality of nodes, para 9; logic nodes based on gate-level netlist, para 32; see netlist, at gate-level and nodes of logic cell, para 43-45; each cell includes a selectably coupled inverter, para 12; each cell is configurable or programmable, para 14), and the programmable logic cell is made programmable to switch inputs and outputs of the logic cell depending on connection relationships of the nodes (see each cell includes a conditional inversion/NOT which is configurable/programmable, para 14; see programmable conditional inversion, Abstract, para 31, 44; using crossbar switch to route any input to any output, para 62; see using crossbar switch to route inputs to outputs based on netlist and graph defining connections for AIG’s, para 62-69).
9. With respect to claim 2, Afshar teaches:
a combinational logic cell composed of a combination of a plurality of the basic logic cells (AIG structure comprises a number of cells, para 12),
wherein the combinational logic cell comprises a plurality of basic logic cells for covering a plurality of nodes constituting a graph of the netlist (see netlist graph defining interconnections of plurality of nodes, para 43-45; see logic blocks with plurality of nodes, para 9; logic nodes based on gate-level netlist, para 32; see netlist, at gate-level and nodes of logic cell, para 43-45; each cell includes a selectably coupled inverter, para 12; see combinational logic synthesis and optimization, para 32; see combinational parts of circuit represented by cells or sub-circuits, para 43-45).
Allowable Subject Matter
10. Claims 3-6 and 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
11. With respect to claim 3 and claims 4-6 which depend therefrom, the prior art made of record fails to teach the combination of steps recited in independent claim 3, including the following particular combination of steps as recited in claim 3, as follows:
wherein the combinational logic cell is a logic cell of (m−1)×n+1 inputs and n outputs, having n of m-input basic logic cells with their input signals switch-ably combined and connected, in order to represent two or more patterns of node connections
12. With respect to claim 8 and claims 9-11 which depend therefrom, the prior art made of record fails to teach the combination of steps recited in independent claim 8, including the following particular combination of steps as recited in claim 8, as follows:
assigning the gate-level netlist to a combinational logic cell composed of a combination of n of m-input basic logic cells,
wherein the combinational logic cell covers n nodes constituting a graph of the netlist; and
configuring the combinational logic cell, the n of m-input basic logic cells, as a logic cell of (m−1)×n+1 inputs and n outputs with their input signals switch-ably combined and connected, in order to represent two or more patterns of connection relationships among the covered plurality of nodes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
Prosecution Insights