DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen(USPGPUB DOCUMENT: 2021/0193813, hereinafter Chen) in view of Sakaniwa (USPGPUB DOCUMENT: 2012/0281487, hereinafter Sakaniwa) and Iwamoto (USPGPUB DOCUMENT: 2010/0187639, hereinafter Iwamoto).
Re claim 1 Chen discloses a common source transistor apparatus, comprising: a common source transistor unit comprising: a diffusion area comprising a plurality of source/bulk areas(216/218) and a plurality of drain areas(216/218) disposed in an interlaced manner(since 216/218 are mixed or combined together this may be interpreted as interlaced); and a plurality of poly-silicon gates(234’)[0052] traversing laterally across the diffusion area, each disposed between one of the source/bulk areas(216/218) and one of the drain areas(216/218) and comprising: a low-voltage gate part(222) comprising 2N low voltage poly-silicon gates(234’)[0052] (since there are pairs or symmetry with respect to the gates, this may be interpreted as 2N) disposed neighboring to each other; and a first high-voltage gate part(340)[0042] and a second high-voltage gate part(340)[0042], the first high-voltage gate part(340)[0042] disposed at a first side of the low-voltage gate part(222) and having one of the source/bulk areas(216/218) disposed between the first high-voltage gate part(340)[0042] and the low-voltage gate part(222) and the second high-voltage gate part(340)[0042] disposed at a second side of the low-voltage gate part(222) and having one of the source/bulk areas(216/218) disposed between the second high-voltage gate part(340)[0042] and the low-voltage gate part(222), wherein each of the first high-voltage gate part(340)[0042] and the second high-voltage gate part(340)[0042] comprises N+1 high-voltage poly-silicon gates(234’)[0052](since there is more than 1 of 234’ this may be interpreted as N+1) disposed neighboring to each other; and a source/bulk ring(216/218) disposed to surround the diffusion area and the poly-silicon gates(234’)[0052] and electrically coupled to the source/bulk areas(216/218); an isolation ring(107a) disposed to surround the transistor unit(326)
Chen does not disclose a source/bulk ring(216/218) disposed to surround the diffusion area and the poly-silicon gates(234’)[0052] and electrically coupled to the source/bulk areas(216/218) to receive a source/bulk voltage; an isolation ring(107a) disposed to surround the common source transistor unit(326) to receive an isolation voltage; and a substrate ring disposed to surround the isolation ring(107a) to receive a substrate voltage; the first high-voltage gate part disposed at a first side of the low-voltage gate part and having one of the source/bulk areas disposed between the first high-voltage gate part and the low-voltage gate part and the second high-voltage gate part disposed at a second side of the low-voltage gate part different from the first side
Sakaniwa disclose a source/bulk voltage[0034 of Sakaniwa]; the common source transistor unit(S2)[0029 of Sakaniwa] to receive an isolation voltage[claim 5 of Sakaniwa]; and a substrate ring(31 of Sakaniwa) to receive a substrate voltage(V)[0062 of Sakaniwa].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Sakaniwa to the teachings of Chen in order to minimize stress increases and failures [0022, Sakaniwa]. In doing so, a source/bulk ring(216/218) disposed to surround the diffusion area and the poly-silicon gates(234’)[0052] and electrically coupled to the source/bulk areas(216/218) to receive a source/bulk voltage; an isolation ring(107a) disposed to surround the common source transistor unit(S2)[0029 of Sakaniwa] to receive an isolation voltage[claim 5 of Sakaniwa]; and a substrate ring(31 of Sakaniwa) disposed to surround the isolation ring(107a) to receive a substrate voltage(V)[0062 of Sakaniwa].
Chen and Sakaniwa does not disclose the first high-voltage gate part disposed at a first side of the low-voltage gate part and having one of the source/bulk areas disposed between the first high-voltage gate part and the low-voltage gate part and the second high-voltage gate part disposed at a second side of the low-voltage gate part different from the first side
Iwamato disclose in Fig 5 the first high-voltage gate part(11a/11b)[0037] disposed at a first side of the low-voltage gate part(11c)[0037] and having one of the source/bulk areas(12/14) disposed between the first high-voltage gate part and the low-voltage gate part and the second high-voltage gate part disposed at a second side of the low-voltage gate part different from the first side
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Iwamato to the teachings of Chen in order to improve the reliability of the device by increasing its breakdown voltage [0009, Iwamato].
Re claim 2 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 1, wherein N is 2, the low-voltage gate part(222) comprises four low voltage poly-silicon gates(234’)[0052], the first high-voltage gate part(340)[0042] comprises three first high voltage poly-silicon gates(234’)[0052] and the second high-voltage gate part(340)[0042] comprises three second high voltage poly-silicon gates(234’)[0052].
Re claim 3 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 1, wherein the low-voltage gate part(222) forms a low voltage transistor[0002] with the corresponding source/bulk areas(216/218) and the corresponding drain areas(216/218), the first high-voltage gate part(340)[0042] and the second high-voltage gate part(340)[0042] form a high voltage transistor[0002] with the corresponding source/bulk areas(216/218) and the corresponding drain areas(216/218), and the low voltage transistor[0002] and the high voltage transistor[0002] share a source.
Re claim 4 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 3, wherein a level of each the source/bulk voltage[0034 of Sakaniwa], the isolation voltage and the substrate voltage corresponds to an operation voltage of the high voltage transistor[0002].
Re claim 5 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 3, wherein the low voltage transistor[0002] has an operation voltage of 5 volts and the high voltage transistor[0002] has an operation voltage 20 volts.
Re claim 6 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 1, wherein the diffusion area is formed on a well area, the well area, the source/bulk ring(216/218) and the isolation ring(107a) are formed on a substrate and the substrate ring is disposed outside of the substrate.
Re claim 7 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 6, wherein the substrate corresponds to a first type dopant[0018], the well area corresponds to a second type dopant[0018], the diffusion area corresponds to the first type dopant[0018] and each of the source/bulk areas(216/218) and the drain areas(216/218) is an ion implantation area corresponding to the first type dopant[0018] and disposed in a doping area comprised by the diffusion area and corresponding to the second type dopant[0018], wherein each of the first type dopant[0018] and the second type dopant[0018] is one of a P-type dopant[0018] and an N-type dopant[0018].
Re claim 8 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 7, wherein each of the source/bulk ring(216/218), the isolation ring(107a) and the substrate ring comprises a bottom part and a planting part disposed above the bottom part, the bottom part and the planting part of each of the source/bulk ring(216/218) and the substrate ring correspond to the second type dopant[0018], and the bottom part and the planting part of the isolation ring(107a) correspond to the first type dopant[0018].
Re claim 9 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 8, wherein an isolation structure is disposed at each of two sides of the planting part of each of the source/bulk ring(216/218), the isolation ring(107a) and the substrate ring.
Re claim 10 Chen and Sakaniwa and Iwamato disclose the common source transistor apparatus of claim 1, wherein the common source transistor(S2)[0029 of Sakaniwa] apparatus comprises a plurality of common source transistor(S2)[0029 of Sakaniwa] unit arranged to be an array so as to be surrounded by the isolation ring(107a).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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