Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 16, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a2) as anticipated ALEKSOV et al.(US 2023/0197770).
Regarding claim 1, ALEKSOV et al. discloses a glass layer(fig 1, 102); a first wiring layer disposed on an upper surface of the glass layer(fig 5, 557); and a capacitor(fig 1, 110) including a plurality of blind holes penetrating through a portion of the glass layer from an upper surface to a lower surface of the glass layer(fig 1, 120), respectively, a first electrode layer disposed on the upper surface of the glass layer and extending into each of the plurality of blind holes(fig 3, 332), a second electrode layer disposed on the first electrode layer and disposed in each of the plurality of blind holes(fig 3, 336), and a first dielectric layer disposed between the first and second electrode layers.(Fig 3, 334).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over ALEKSOV et al.(US 2023/0197770).
Regarding claim 2, ALEKSOV et al. does not disclose the upper surface of the glass layer, the first wiring layer, the first electrode layer, and the second electrode layer have different thicknesses. It would have been obvious to one of ordinary skill to modify the circuit board of Lee, to include an upper surface of the glass layer, the first wiring layer, the first electrode layer, and the second electrode layer have different thicknesses since it has been held that the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 3, ALEKSOV et al. does not disclose wherein the upper surface of the glass layer, the first wiring layer is thicker than the second electrode layer, and the second electrode layer is thicker than the first electrode layer. It would have been obvious to one of ordinary skill to modify the circuit board of Lee, to include an upper surface of the glass layer, the first wiring layer is thicker than the second electrode layer, and the second electrode layer is thicker than the first electrode layer, since it has been held that the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 14-20, 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lasiter et al. (US 8896521 B2) in view of Burns et al. (US 20120235969 A1)
Regarding Claim 1 – Lasiter teaches a printed circuit board (Fig 13D; 1300) comprising: a glass layer (Fig 13D; 1302; Lasiter [Detailed description] states “glass substrate 1302”); and a capacitor including a plurality of blind holes penetrating through a portion of the glass layer from an upper surface to a lower surface of the glass layer (Figs 11A/11B show an array of vias 1102; Fig 10A; Lasiter states “the glass substrate 1002 may define a plurality of vias… the via 1004 may be a blind via; i.e., the via 1004 may be a via that does not pass completely through the glass substrate 1002”), respectively, a first electrode layer disposed on the upper surface of the glass layer and extending into each of the plurality of blind holes (Fig 9 ; Lasiter states “a first electrode layer is deposited over surfaces of the glass substrate… including surfaces of the at least one via” and Fig 12; 1204 flowchart states “Deposit a first electrode layer over surfaces of the glass substrate”), a second electrode layer disposed on the first electrode layer and disposed in each of the plurality of blind holes (Fig 9; Lasiter states “at block 908 a second electrode layer is deposited on the dielectric layer” and Fig 12; 1208 flowchart states “Deposit a second electrode layer on the dielectric layer”), and a first dielectric layer disposed between the first and second electrode layers (Fig 10D; Lasiter states “The dielectric layer 1020 may electrically isolate the first electrode layer 1016 from the second electrode layer 1024” and Fig 12; 1206 flowchart states “Deposit a dielectric layer on the first electrode layer”).
However, Lasiter does not explicitly disclose a first wiring layer disposed on an upper surface of the glass layer; rather, the cited portions describe pads on passivation and an interconnect associated with a through glass via (Figs 13D/13E; Lasiter states “at block 1212 interconnect pads are plated on the passivation layer” and “The second electrode layer 1330 may form an interconnect associated with the through glass via 1306”).
Burns teaches a first wiring layer disposed on an upper surface of the glass layer (Fig 9A; Burns [0084] states “conductive topside trace 94a on top surface 92a”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed circuit board of Lasiter with a first wiring layer disposed on an upper surface of the glass layer as taught by Burns to get the benefit of providing electrical interconnection on the glass surface using conductive traces, Burns [0084] states “The MEMS and IC devices can be electrically connected to one or more through-glass vias 93 directly or indirectly by topside traces 94a on glass substrate 91”.
Regarding Claim 2 – Lasiter in view of Burns teaches the printed circuit board according to claim 1, wherein on the upper surface of the glass layer, the first wiring layer, the first electrode layer, and the second electrode layer have different thicknesses (Lasiter Fig 10D teaches the thicknesses for the electrode layers disposed on the glass substrate; Lasiter states “the first electrode layer 1016 may be about 0.5 microns to 20 microns thick” and “the second electrode layer 1024 may be about 0.5 microns to 50 microns thick… In some other implementations, the first electrode layer 1016 and the second electrode layer 1024 may have different thicknesses”; Additionally, Burns Fig 11B teaches thicknesses for conductive wiring layers formed on a glass substrate surface using thin film + plating; Burns [0099] states “the plated layer thickness is between 3 and 30 microns” and Burns [0100] states “Thicknesses of the thin films… may range from less than 0.05 to over 5 microns”; Lasiter teaches that the first and second electrode layers may be formed with different thicknesses, and Burns teaches that the wiring layer thickness is selectable and may differ from the electrode thickness).
Regarding Claim 3 – Lasiter in view of Burns teaches the printed circuit board according to claim 2, wherein on the upper surface of the glass layer, the first wiring layer is thicker than the second electrode layer, and the second electrode layer is thicker than the first electrode layer (Lasiter Fig 10D and Burns Fig 11B quoted above expressly disclose fabricating conductive layers on glass substrates with selectable thicknesses e.g., selecting the wiring plating thickness from the upper portion of Burns’ disclosed range and selecting electrode thicknesses from lower portions of Lasiter’s ranges such that the second electrode is thicker than the first electrode).
Regarding Claim 4 – Lasiter in view of Burns teaches the printed circuit board according to claim 1, wherein at least a part of the first electrode layer extends along the upper surface of the glass layer so as not to be covered with the second electrode layer (Fig 12; 1202-1208 flowchart state “Deposit a first layer over surfaces of the glass substrate” then “Deposit a second electrode layer on the dielectric layer”, Lasiter further states “a dry film mask may be used to define the regions of the dielectric layer onto which the second electrode layer is deposited” If the second electrode is deposited only onto mask-defined regions of the dielectric, then portions of the first electrode footprint necessarily remain outside those regions, i.e., not covered by the second electrode layer).
Regarding Claim 5 – Lasiter in view of Burns teaches the printed circuit board according to claim 1, wherein the first wiring layer comprises: a first seed layer disposed on the upper surface of the glass layer (Fig 11B; 101; Burns [0098] states “the thin film 101 is also deposited on the top and bottom surfaces of glass substrate 91” and Burns [0099] states “If plating is performed, the layers deposited in operation 115 may be used as seed layers for the subsequent plating operation 117”); and a first metal layer disposed on an upper surface of the first seed layer (Fig 11B; Burns [0099] states “FIG. 11B shows a plated layer 102 over thin film 101” additionally, Burns [0098] states “thin film 101 may be selectively patterned and etched… to form, for example, electrical traces… and other connective features”).
Regarding Claim 6 – Lasiter in view of Burns teaches the printed circuit board according to claim 5, wherein on the upper surface of the glass layer, the first seed layer has substantially the same thickness as the first electrode layer, and the first metal layer is thicker than the second electrode layer (Lasiter Fig 10D and Burns Fig 11B quoted above expressly disclose fabricating conductive layers on glass substrates with selectable thicknesses e.g., selecting the seed (thin film) thickness from Burns’ disclosed range and selecting the first electrode thickness from Lasiter’s disclosed range such that the first seed layer has substantially the same thickness as the first electrode layer, and selecting the first metal thickness from the upper portion of Burns’ disclosed range and selecting the second electrode’s thickness from a lower portion of Lasiter’s disclosed range such that the first metal layer is thicker than the second electrode layer).
Regarding Claim 7 – Lasiter in view of Burns teaches the printed circuit board according to claim 5, further comprising: a second wiring layer disposed on the lower surface of the glass layer (Fig 9A; 94b; Burns [0084] states “Conductive bottomside traces 94b on bottom surface 92b”), wherein the second wiring layer comprises: a second seed layer disposed on the lower surface of the glass layer (Fig 11B; 101; Burns [0098] states “the thin film 101 is also deposited on the top and bottom surfaces of glass substrate 91” and Burns [0099] states “the layers deposited in operation 115 may be used as seed layers for the subsequent plating operation 117”); and a second metal layer disposed on a lower surface of the second seed layer (Fig 11B; Burns [0099] states “FIG. 11B shows a plated layer 102 over thin film 101”).
Regarding Claim 14 – Lasiter in view of Burns teaches the printed circuit board according to claim 1, wherein the second electrode layer comprises: a fifth seed layer disposed on the first dielectric layer; and a fourth metal layer disposed on the fifth seed layer and disposed in each of the plurality of blind holes (Fig 9; Lasiter states “the second electrode layer may be deposited using… a plating process, as described above with respect to the first electrode layer” and Lasiter further states “the seed layer may be about 25 nanometers (nm) to 500 nm thick. After the seed layer is deposited, the first electrode layer may be deposited using a plating process, with the seed layer acting as a nucleation site”), and on the upper surface of the glass layer, the fourth metal layer is thicker than the fifth seed layer (Lasiter seed thickness 25 nm to 500 nm; and electrode thickness “the first electrode layer 1016 may be about 0.5 microns to 20 microns thick”).
Regarding Claim 15 – Lasiter in view of Burns teaches the printed circuit board according to claim 1, wherein the glass layer includes plate glass (Fig 11A; Burns [0094] states “a glass substrate (sometimes referred to as a glass plate or panel)”).
Regarding Claim 16 – Lasiter in view of Burns teaches the printed circuit board according to claim 1, wherein an upper surface of the first wiring layer is disposed on a different level from an upper surface of the second electrode layer (Burns Fig 11B quoted above teaches plated thickness and film thicknesses are selectable and Lasiter Fig 10D quoted discloses electrode thickness ranges; Since Burns’ wiring height and Lasiter’s electrode height is selectable, selecting different thicknesses necessarily places their upper surfaces at different levels).
Regarding Claim 17 – Lasiter in view of Burns teaches the printed circuit board according to claim 1, wherein the first electrode layer is in contact with the glass layer (Fig 10D; Lasiter states “The MIM capacitor 1000 includes the glass substrate 1002, the first electrode layer 1016” showing the first electrode layer formed on the glass substrate; see also Burns Fig 11B; Burns [0098] states “Thin film 101 coats the sidewalls… continuously… the thin film 101 is also deposited on the top and bottom surfaces of glass substrate 91” which places the conductive layer directly on the glass substrate surfaces).
Regarding Claim 18 – Lasiter teaches a printed circuit board (Fig 13D; 1300) comprising: a glass layer (Fig 13D; 1302; Lasiter [Detailed description] states “glass substrate 1302”); a through-hole penetrating through the glass layer from an upper surface to a lower surface of the glass layer (Fig 13A; Lasiter states “the glass substrate 1302 may define… at least one through glass via 1306”; Fig 12; 1202 flowchart states “Form at least one via and at least one through glass via in a glass substrate”); a plurality of blind holes respectively penetrating through a portion of the glass layer from the upper surface to the lower surface of the glass layer (Figs 10A/11A-11B; Lasiter states “the glass substrate 1002 may define a plurality of vias” and “In some other implementations, the via 1004 may be a blind via… does not pass completely through the glass substrate 1002”); a third conductor layer disposed on the first conductor layer and disposed in the through-hole and each of the plurality of blind holes (Fig 10A/13D; Lasiter states “The MIM capacitor 1000 includes… the first electrode layer 1016, the dielectric layer 1020, and a second electrode layer 1024” are disposed within the same via 1004; see also Fig 12; 1028 flowchart states “Deposit a second electrode layer on the dielectric layer”); and a dielectric layer disposed between the first and third conductor layers, on the upper surface of the glass layer, the wall surface of the through-hole, and the wall surface and the bottom surface of each of the plurality of blind holes (Fig 10D; Lasiter states “The dielectric layer 1020 may electrically isolate the first electrode layer 1016 from the second electrode layer 1024”; Fig 12; 1206 flowchart states “Deposit a dielectric layer on the first electrode layer”).
Lasiter fails to explicitly disclose a first conductor layer disposed on the upper surface and the lower surface of the glass layer and extending onto a wall surface of the through-hole and a wall surface and a bottom surface of each of the plurality of blind holes (Figs 10A/12; 1204; Lasiter states “depositing a first electrode layer over regions of the first surface of the glass substrate… including on portions of the first electrode layer in the first vias”).
Burns teaches a first conductor layer disposed on the upper surface and the lower surface of the glass layer and extending onto a wall surface of the through-hole and a wall surface and a bottom surface of each of the plurality of blind holes (Fig 11B; Burns [0098] states “Thin film 101 coats the sidewalls… continuously from the top surface to the bottom surface of glass substrate 91” and “the thin film 101 is also deposited on the top and bottom surfaces of glass substrate 91”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed circuit board of Lasiter with a first conductor layer disposed on the upper surface and the lower surface of the glass layer and extending onto a wall surface of the through-hole and a wall surface and a bottom surface of each of the plurality of blind holes as taught by Burns because Burns teaches that the conductive thin film “provide conductive paths through the via” (Burns [0103]) thereby improving electrical continuity and interconnection.
Regarding Claim 19 – Lasiter in view of Burns teaches the printed circuit board according to claim 18, wherein the third conductor layer comprises: a third-first conductor layer disposed on at least a portion of the first conductor layer and disposed in the through-hole and each of the plurality of blind holes (Lasiter Figs 9/10A; block 908, via 1004; Lasiter states “at block 908 a second electrode layer is deposited on the dielectric layer… the second electrode layer may be deposited using a… plating process”, Lasiter further states “a seed layer may first be deposited over surfaces of the glass substrate” and “the seed layer may be about 25 nanometers (nm) to 500 nm thick”); and a third-second conductor layer disposed on at least another portion of the first conductor layer and covering a portion of the third-first conductor layer disposed in the through-hole, (Burns Fig 11B; Burns [0099] states “one or more additional metal layers are formed by… electroplating on the conductive thin film”) and on the upper surface of the glass layer, the third-second conductor layer is thicker than the third-first conductor layer (Burns [0099] states “plated layer thickness is between 3 and 30 microns” and Burns [0100] states “Thicknesses of the thin films… may range from less than 0.05 to over 5 microns”).
Regarding Claim 20 – Lasiter in view of Burns teaches the printed circuit board according to claim 19, wherein at least another portion of the first conductor layer extends along the upper surface of the glass layer so as not to be covered with the third-first conductor layer (Lasiter Fig 9; 904; Lasiter states “a dry film mask may be used to define the regions of the glass substrate onto which the first electrode layer is deposited”; see also Burns Fig 11B; thin film 101 as the initial conductor used for plating).
Regarding Claim 22 – Lasiter in view of Burns teaches the printed circuit board according to claim 18, wherein the first conductor layer is in contact with the glass layer (Lasiter Fig 10A; 904 flowchart states “Deposit a first electrode layer over the surfaces of the glass substrate” (including via surfaces); see also Burns Fig 11B; Burns [0098] states “the thin film 101 is also deposited on the top and bottom surfaces of glass substrate 91”).
Claims 8-12, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lasiter et al. (US 8896521 B2) in view of Burns et al. (US 20120235969 A1) and in further view of Volant et al. (US 20110095435 A1)
Regarding Claim 8 – Lasiter in view of Burns teaches the printed circuit board according to claim 7, further comprising: a through-via penetrating through the glass layer and connecting at least a portion of each of the first and second wiring layers to each other (Fig 9A; Burns [0084] states “A through-glass via 93… provides a conductive pathway between portions of top surface 92a and bottom surface 92b” and “conductive topside trace 94a” and “Conductive bottomside traces 94b”), wherein the through-via comprises: a through-hole penetrating through the glass layer from the upper surface to the lower surface of the glass layer (Fig 9A; 93 in 91; Burns [0084] states “glass substrate 91.. top surface 92a and bottom surface 92b… through-glass vias 93 formed therein… provides a conductive pathway… through glass substrate 91”); a third seed layer disposed on a wall surface of the through-hole (Fig 11B; Burns [0098] states “FIG. 11B shows thin film 101 coating the sidewalls of through-glass via hole 122 at 130… continuously from the top surface to the bottom surface”);
Lasiter in view of Burns does not explicitly disclose a second dielectric layer disposed on the third seed layer; a fourth seed layer disposed on the second dielectric layer, and a third metal layer disposed on the fourth seed layer and disposed in the through-hole.
Volant teaches a second dielectric layer disposed on the third seed layer (Figs 4/5; Volant [0042] states “after depositing on all exposed surfaces electrically insulating material… insulator outer wall 70, insulator inner wall 70a, and insulator top surface 70b” and Volant [0043] states “a dielectric film covering the sidewalls of the via 30”); a fourth seed layer disposed on the second dielectric layer (Fig 6; Volant [0044] states “a liner and seed conformal deposition required for Cu plating” and Volant [0019] states “conformally depositing a liner and a seed for copper plating”), and a third metal layer disposed on the fourth seed layer and disposed in the through-hole (Fig 6; Volant [0044] states “a conformal plated Cu layer” identifies the plated conductors “The conductor 50… element 60” and describes them in the context of the conformal plated Cu layer).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed circuit board of Lasiter in view of Burns with a second dielectric layer disposed on the third seed layer; a fourth seed layer disposed on the second dielectric layer, and a third metal layer disposed on the fourth seed layer and disposed in the through-hole as taught by Volant because Volant teaches the dielectric liner step is used “to electrically isolate the substrate from any conductive material… and to reduce the migration of conductive material into the substrate” (Volant [0042]). Since Burns forms the thin film/seed layer on the through-wall surface, Volant’s deposition “on all exposed surfaces” would deposit the insulating material on the exposed thin film/seed layer.
Regarding Claim 9 – Lasiter in view of Burns and Volant teaches the printed circuit board according to claim 8, wherein the first and second dielectric layers include the same insulating material (Fig 10D; Lasiter states “The dielectric layer 1020 may electrically isolate the first electrode layer 1016 from the second electrode layer 1024”; and, Figs 4-5; Volant [0042] states “after depositing on all exposed surfaces electrically insulating material”, Volant [0043] states “a dielectric film covering the sidewalls of the via 30”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed circuit board of Lasiter in view of Burns with the first and second dielectric layers include the same insulating material as taught by Volant because both layers perform the same fundamental function of electric isolation between conductive layers.
Regarding Claim 10 – Lasiter in view of Burns and Volant teaches the printed circuit board according to claim 8, wherein no boundary exists at connection portions between each of the first and second seed layers and the third seed layer (Fig 11B; Burns [0098] states “Thin film 101 coats the sidewalls… continuously from the top surface to the bottom surface of glass substrate 91… the thin film 101 is also deposited on the top and bottom surfaces of glass substrate 91”), and a boundary exists at connection portions between each of the first and second metal layers and the third metal layer (Fig 11A; Burns [0099] states plated layer 102 is “plated over continuous thin film 101” and is “also continuous from the top surface to the bottom surface” and further that “Plated materials may be used to fill or partially fill the via hole”).
Regarding Claim 11 – Lasiter in view of Burns and Volant teaches the printed circuit board according to claim 8, wherein with respect to the upper surface of the glass layer, at least a portion of each of the fourth seed layer and the third metal layer protrudes further upwardly than each of the third seed layer and the second dielectric layer (Figs 4-5; Volant [0042] states “after depositing on all exposed surfaces electrically insulating material… insulator… and insulator top surface 70b”; Fig 6; Volant [0044] states “there is shown a liner and seed conformal deposition required for Cu plating and a conformal plated Cu layer… Element 55… is referred as the Cu overburden which subsequently is removed”; Fig 10; Volant [0048] states “performing a chemical-mechanical polish (CMP)… to remove the Cu overburden… while making the entire structure(s) substantially planar” Because Volant forms Cu overburden 55 over the insulator top surface 70b and then removes it by CMP, the Cu/seed stack protrudes further upwardly than the dielectric prior to CMP), and with respect to the lower surface of the glass layer, at least another portion of each of the fourth seed layer and the third metal layer protrudes further downwardly than each of the third seed layer and the second dielectric layer (Fig 11; Volant [0049] states “the backside… is substantially thinned out… in order to expose the bottom portion of the vias”; Fig 12; Volant [0050] states “addition of a conformal dielectric layer 250 deposition on the backside”; Fig 13; Volant [0051] states “the CMP… intended to remove any protruding portions of the vias, leaving the dielectric 250 and the via structures substantially planar”).
Regarding Claim 12 – Lasiter in view of Burns and Volant teaches the printed circuit board according to claim 11, wherein a further protruding thickness of at least a portion and at least another portion of each of the fourth seed layer and the third metal layer are substantially identical to a thickness of each of the first dielectric layer and the second dielectric layer (Fig 11; Volant [0061] states “The wafer is then back-side thinned to expose the bottom of the TSVs such that they protrude from the back surface. The amount of protrusion should be equal to or be greater than… added to the via insulating layer”).
Regarding Claim 21 – Lasiter in view of Burns teaches the printed circuit board according to claim 19, but doesn’t explicitly disclose further comprising: a second conductor layer disposed between the dielectric layer and the third-first conductor layer.
Volant teaches a second conductor layer disposed between the dielectric layer and the third-first conductor layer (Fig 6; Volant [0044] states “there is shown a liner and seed conformal deposition required for Cu plating” wherein the liner is deposited before the seed, such that the liner is disposed between the dielectric layer and the seed layer).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed circuit board of Lasiter in view of Burns with a second conductor layer disposed between the dielectric layer and the third-first conductor layer as taught by Volant because Volant expressly describes the liner + seed as “required for Cu plating” (Volant [0044]) to ensure reliable plated conductor formation in the via environment.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lasiter et al. (US 8896521 B2) in view of Burns et al. (US 20120235969 A1) and Volant et al. (US 20110095435 A1) and in further view of Rho et al. (US 20210398891 A1) and Kim et al. (US 20170154838 A1)
Regarding Claim 13 – Lasiter in view of Burns and Volant teaches the printed circuit board according to claim 8, but doesn’t explicitly disclose further comprising: one or more first build-up insulating layers disposed on the upper surface of the glass layer; one or more first build-up wiring layers respectively disposed on or inside the one or more first build-up insulating layers; one or more first build-up via layers respectively penetrating through at least one of the one or more first build-up insulating layers; one or more second build-up insulating layers disposed on the lower surface of the glass layer; one or more second build-up wiring layers respectively disposed on or inside the one or more second build-up insulating layers; one or more second build-up via layers respectively penetrating through at least one of the one or more second build-up insulating layers; a first resist layer disposed on a first build-up insulating layer disposed on an uppermost side of the one or more first build-up insulating layers; and a second resist layer disposed on a second build-up insulating layer disposed on a lowermost side of the one or more second build-up insulating layers.
Rho teaches one or more first build-up insulating layers disposed on the upper surface of the glass layer (Fig 5; Rho [0134] states “An upper layer 26 is disposed on the first surface 213”; Rho [0135] states “upper insulating layer 253 disposed on the first surface”; Rho [0138] states “plural-layered insulating layers… are collectively referred to as an upper insulating layer”); one or more first build-up wiring layers respectively disposed on or inside the one or more first build-up insulating layers (Fig 5; 251; Rho [0136] states “an upper distribution pattern 251… built in the upper insulting layer”); one or more first build-up via layers respectively penetrating through at least one of the one or more first build-up insulating layers (Fig 5; 252; Rho [0136] states “a blind via 252… built in the upper insulting layer”); one or more second build-up insulating layers disposed on the lower surface of the glass layer (Fig 5; 29/214/291b; Rho [0152] states “A lower insulating layer 291b is an insulating layer at least a part of which is in contact with the second surface 214”); one or more second build-up wiring layers respectively disposed on or inside the one or more second build-up insulating layers (Fig 5; Rho [0151-0152] states “The lower distribution layer 291 includes a lower insulating layer 291b; and a lower distribution pattern 291a” and that the pattern is “embedded in the lower insulating layer”); a first resist layer disposed on a first build-up insulating layer disposed on an uppermost side of the one or more first build-up insulating layers (Fig 5; Rho [0135] states “The uppermost surface of the upper layer 26 may be protected by a cover layer 60 having an opening part formed thereon”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed circuit board of Lasiter in view of Burns and Volant with one or more first build-up insulating layers disposed on the upper surface of the glass layer; one or more first build-up wiring layers respectively disposed on or inside the one or more first build-up insulating layers; one or more first build-up via layers respectively penetrating through at least one of the one or more first build-up insulating layers; one or more second build-up insulating layers disposed on the lower surface of the glass layer; one or more second build-up wiring layers respectively disposed on or inside the one or more second build-up insulating layers; a first resist layer disposed on a first build-up insulating layer disposed on an uppermost side of the one or more first build-up insulating layers as taught by Rho because Fig 5; Rho [0139] teaches the “build-up layer method” by “repeating” forming insulating layers and forming conductive layers by plating (i.e., build-up wiring/vias) on the substrate.
Kim teaches one or more second build-up via layers respectively penetrating through at least one of the one or more second build-up insulating layers (Fig 26; Kim [0135] states “redistribution layers… maybe electrically connected… through vias 113a and 113b”); and a second resist layer disposed on a second build-up insulating layer disposed on a lowermost side of the one or more second build-up insulating layers (Fig 23; Kim [0127] states “insulating layers 111a and 112b… may be further disposed on an upper surface and/or a lower surface”; and Kim [0124] states “various patterns 112a and 112b may be disposed on an upper surface and a lower surface”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed circuit board of Lasiter in view of Burns and Volant with one or more second build-up via layers respectively penetrating through at least one of the one or more second build-up insulating layers; and a second resist layer disposed on a second build-up insulating layer disposed on a lowermost side of the one or more second build-up insulating layers as taught by Kim because Figs 22-23; Kim teaches patterns on both sides and explains that having wiring on both upper and lower surfaces provides “a wider routing region” and improves “degree of freedom”.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a2) as anticipated ALEKSOV et al.(US 2023/0197770).
Regarding claim 1, ALEKSOV et al. discloses a glass layer(fig 1, 102); a first wiring layer disposed on an upper surface of the glass layer(fig 5, 557); and a capacitor(fig 1, 110) including a plurality of blind holes penetrating through a portion of the glass layer from an upper surface to a lower surface of the glass layer(fig 1, 120), respectively, a first electrode layer disposed on the upper surface of the glass layer and extending into each of the plurality of blind holes(fig 3, 332), a second electrode layer disposed on the first electrode layer and disposed in each of the plurality of blind holes(fig 3, 336), and a first dielectric layer disposed between the first and second electrode layers.(Fig 3, 334).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over ALEKSOV et al.(US 2023/0197770).
Regarding claim 2, ALEKSOV et al. does not disclose the upper surface of the glass layer, the first wiring layer, the first electrode layer, and the second electrode layer have different thicknesses. It would have been obvious to one of ordinary skill to modify the circuit board of Lee, to include an upper surface of the glass layer, the first wiring layer, the first electrode layer, and the second electrode layer have different thicknesses since it has been held that the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 3, ALEKSOV et al. does not disclose wherein the upper surface of the glass layer, the first wiring layer is thicker than the second electrode layer, and the second electrode layer is thicker than the first electrode layer. It would have been obvious to one of ordinary skill to modify the circuit board of Lee, to include an upper surface of the glass layer, the first wiring layer is thicker than the second electrode layer, and the second electrode layer is thicker than the first electrode layer, since it has been held that the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847