DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered.
Election/Restrictions
Applicant's election with traverse of Invention I (claims 1-11) and species of Figure 4 in the reply filed is acknowledged. The traversal is on the ground(s) that burden is lacking. Applicant has not provided any specific support for this argument.
Applicant has identified claims 1-12 as readable thereon. However, claims 8-11 are drawn to non elected species of Figure 7. Further, claim 12 is a linking claim. Therefore an action on the merits of claims 1-7 and 12 follows and claims 8-11 and 13-20 stand withdrawn. Applicant is reminded that in order to maintain claim 12 as a linking claim similar amendments as any to claim 1 should be made.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (US 2024/0112742).
Regarding claim 1, Huang discloses an apparatus, comprising: an array of memory cells (see Figure 2); and a controller coupled to the array of memory cells (70), wherein the controller is configured to: apply a first erase voltage (see Figure 6, S610 Veras0) to a first wordline and a second wordline in the array of memory cells to perform an erase operation (applied to all word lines in the block); apply a first verify voltage (EV1 in step 630) to the first wordline to verify the erase operation; apply a second verify voltage (EV2 in step 640) greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline (635 No); and apply a second erase voltage (step 670) to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline (665 Y).
Regarding claim 2, Huang discloses the apparatus of claim 1, wherein the first wordline is an even wordline and the second wordline is an odd wordline (the labeling of Even and Odd is purely descriptive since the claims direct no relative structure).
Regarding claim 3, Huang discloses the apparatus of claim 1, wherein the first wordline is an odd wordline and the second worline is an even wordline (the labeling of Even and Odd is purely descriptive since the claims direct no relative structure).
Regarding claim 4, Huang discloses the apparatus of claim 1, wherein the second erase voltage equals a sum of the first erase voltage (Verase) and a verify voltage increment value (the increase).
Regarding claim 5, Huang discloses the apparatus of claim 1, wherein the controller is configured to apply the first verify voltage to the second wordline in response to verifying the erase operation by applying the first verify voltage to the first wordline (635 Yes).
Regarding claim 6, Huang discloses the apparatus of claim 5, wherein the controller is configured to complete the erase operation in response to verifying the erase operation by applying the first verify voltage to the second wordline (S680).
Regarding claim 7, Huang discloses the apparatus of claim 1, wherein the controller is configured to verify the erase operation in response to a failing bit count from applying the second verify voltage being zero (see paragraph 0065).
Regarding claim 12, Huang discloses a method, comprising: applying a first erase voltage to an even wordline and an odd wordline in an array of memory cells to perform an erase operation; applying a first verify voltage to the even wordline to verify the erase operation; applying a second verify voltage greater than the first verify voltage to the odd wordline in response to failing to verify the erase operation by applying the first verify voltage to the even wordline; and applying a second erase voltage to the even wordline and the odd wordline in response to verifying the erase operation by applying the second verify voltage to the odd wordline (see rejections of claims 1 and 3 above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The remaining cited and attached references teach various embodiments of erase verify schemes in memory devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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