CTFR 18/443,733 CTFR 90500 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted 4/1/2025, 8/6/2025 being considered by the examiner. 12-151 AIA 26-51 12-51 Status of Claims This office action is in response to "Claims filed on 5/12/2026". Applicant's amendments of claims 1, 2, 11, 12, 14 with the same reply have been entered by the Examiner. Upon entry of the amendments, claims 1-20 are pending wherein claim 1 is independent. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Huang, Chih-Wei (US 2021/0407908 A1 hereinafter Huang) . Regarding Claim 1, Huang discloses in Fig 1B: A semiconductor device, comprising: a substrate (100) having an active region (AA) and a trench (RS); a recess gate structure (104) disposed in the substrate and intersecting the active region (See Fig 1B); a conductive pillar (116) disposed over the substrate and electrically connected to the active region (See Fig 1B); a landing pad (CP) disposed on the conductive pillar and electrically connected to the conductive pillar (116); and a stack of dielectric layers (110: See Fig 3J) disposed over the substrate (100) and laterally surrounding the conductive pillar and the landing pad; wherein the recess gate structure comprises a gate insulating layer (106) conformally formed in the trench of the substrate and formed on side surfaces and a bottom surface of the trench (RS); wherein a top surface of the gate insulating layer is coplanar with a top surface of the substrate (100). [0018-0023] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 2-4, 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Cheng et al (US 2022/0037510 A1 hereinafter Cheng) . Regarding Claim 2, Huang discloses in Fig 1B: The semiconductor device of claim 1, wherein the recess gate structure further comprises: a first conductive layer (WL) formed on the work function layer and in the trench; and a capping layer (108) formed on the first conductive layer and in the trench (See Fig 1B); wherein the first conductive layer, and the capping layer are surrounded by the gate insulating layer (106); wherein the top surface of the gate insulating layer (106), a top surface of the capping layer (108), and the top surface of the substrate (100) are coplanar with each other. Huang does not disclose: a work function layer formed on the gate insulating layer and in the trench. However, Cheng in a similar device teaches in Fig 1B: a work function layer (140) formed on the gate insulating layer (136/138) and in the trench. References Huang and Cheng are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang with the specified features of Cheng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Cheng so that a work function layer formed on the gate insulating layer and, in the trench, as taught by Cheng in Huang’s device since, this improves the integrity of the gate structure [0019]. Regarding Claim 3, Huang and Cheng disclose: The semiconductor device of claim 2, wherein the gate insulating layer (106) is formed by a thermal oxidation process. The limitation “formed by a thermal oxidation process” in claim 3 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in “product by process” claim or not. Regarding Claim 4, Huang and Lin disclose: The semiconductor device of claim 3, Huang further discloses in Fig 1B: wherein the gate insulating layer includes a high-k material such as an oxide, a nitride, an oxynitride, or a combination thereof [0024]. Regarding Claim 9, Cheng discloses in Fig 1B: The semiconductor device of claim 2, wherein the capping layer is formed of germanium oxide [0035]. Regarding Claim 10, Huang and Cheng disclose: The semiconductor device of claim 9, The limitation “wherein the capping layer is formed by chemical vapor deposition, atomic layer deposition or another applicable deposition process.” in claim 10 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in “product by process” claim or not. Regarding Claim 11, Huang and Cheng disclose: The semiconductor device of claim 2, Huang discloses in Fig 1B: wherein the top surface of the capping layer (108), and the top surface of the substrate (100) are in contact (indirect contact) with a bottom surface of the stack of dielectric layers (110). Regarding Claim 12, Huang and Cheng disclose: The semiconductor device of claim 11, Huang discloses in Fig 1B: the active region (AA) is in contact with the bottom surface of the stack of dielectric layers (110). Regarding Claim 13, Huang and Cheng disclose: The semiconductor device of claim 12, Huang discloses in Fig 1B: wherein a bottom surface of the capping layer (108) is located at a vertical level higher than a bottom surface of the active region (AA). Regarding Claim 14, Huang and Cheng disclose: The semiconductor device of claim 2, Huang discloses in Fig 1B: wherein a top surface of the gate insulating layer (106) is at a vertical level higher than a bottom surface of the active region (AA). Regarding Claim 15, Huang and Cheng disclose: The semiconductor device of claim 14. Huang does not disclose: wherein the top surface of the gate insulating layer and a bottom surface of the capping layer are substantially coplanar. However, Cheng in a similar device discloses in Fig 1B: wherein the top surface of the gate insulating layer (114/138) and a bottom surface of the capping layer (148) are substantially coplanar (See Fig 1B). References Huang and Cheng are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang with the specified features of Cheng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Cheng so that the top surface of the gate insulating layer and a bottom surface of the capping layer are substantially coplanar, as taught by Cheng in Huang’s device since, this improves the integrity of the gate structure [0019]. Regarding Claim 16, Huang and Cheng disclose: The semiconductor device of claim 14. Huang does not disclose: further comprising: a liner layer conformally disposed on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and a second conductive layer disposed between the capping layer and the liner layer. However, Cheng in a similar device discloses in Fig 1B further comprising: a liner layer (150) conformally disposed on the first conductive layer (144) and on the gate insulating layer (114/138), and disposed between the capping layer (148) and the first conductive layer (144); and a second conductive layer (152) disposed between the capping layer (148) and the liner layer (150) [0040]. References Huang and Cheng are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang with the specified features of Cheng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Cheng so that a liner layer conformally disposed on the first conductive layer and on the gate insulating layer, and disposed between the capping layer and the first conductive layer; and a second conductive layer disposed between the capping layer and the liner layer as taught by Cheng in Huang’s device since, this improves the integrity of the gate structure [0019]. Regarding Claim 17, Huang and Cheng disclose: The semiconductor device of claim 16. Huang does not disclose: wherein the liner layer includes a U-shaped cross-sectional profile. However, Cheng in a similar device discloses in Fig 1B further comprising: wherein the liner layer (150) includes a U-shaped cross-sectional profile [0040-0041]. References Huang and Cheng are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang with the specified features of Cheng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Cheng so that the liner layer includes a U-shaped cross-sectional profile as taught by Cheng in Huang’s device since, this improves the integrity of the gate structure [0019]. Regarding Claim 18, Huang and Cheng disclose: The semiconductor device of claim 16. Huang does not disclose: wherein a top surface of the liner layer is substantially coplanar with a bottom surface of the capping layer. However, Cheng in a similar device discloses in Fig 1B further comprising: wherein a top surface of the liner layer (150) is substantially coplanar with a bottom surface of the capping layer (150) [0040]. References Huang and Cheng are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang with the specified features of Cheng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Cheng so that a top surface of the liner layer is substantially coplanar with a bottom surface of the capping layer as taught by Cheng in Huang’s device since, this improves the integrity of the gate structure [0019]. Regarding Claim 19, Huang and Cheng disclose: The semiconductor device of claim 18. Huang does not disclose: wherein a top surface of the second conductive layer and a bottom surface of the capping layer are substantially coplanar. However, Cheng in a similar device discloses in Fig 1B further comprising: wherein a top surface of the second conductive layer (152) and a bottom surface of the capping layer are substantially coplanar (148) [0040]. References Huang and Cheng are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang with the specified features of Cheng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Cheng so that a top surface of the second conductive layer and a bottom surface of the capping layer are substantially coplanar as taught by Cheng in Huang’s device since, this improves the integrity of the gate structure [0019]. Regarding Claim 20, Huang and Cheng disclose: The semiconductor device of claim 19. Huang does not disclose: wherein the liner layer (150 can include a nitride material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), other suitable nitride materials) is formed of a material having an etching selectivity (different materials have different etching sensitivities) to the gate insulating layer (114/138) silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide/HK layer). However, Cheng in a similar device discloses in Fig 1B further comprising: wherein the liner layer (150 can include a nitride material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), other suitable nitride materials) is formed of a material having an etching selectivity (different materials have different etching sensitivities) to the gate insulating layer (114/138) silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide/HK layer) [0022, 0033]. References Huang and Cheng are analogous art because they both are directed to memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang with the specified features of Cheng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang and Cheng so that wherein the liner layer (150 can include a nitride material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), other suitable nitride materials) is formed of a material having an etching selectivity (different materials have different etching sensitivities) to the gate insulating layer (114/138) silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide/HK layer) as taught by Cheng in Huang’s device since, this improves the integrity of the gate structure [0019] . 07-21-aia AIA Claim (s) 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Cheng and further in view of Chien et al (US 2020/0006566 A1 hereinafter Chien) . Regarding Claim 5, Huang and Cheng disclose: The semiconductor device of claim 2. Huang and Cheng do not disclose: wherein the work function layer is formed of doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. However, Chien in a similar device teaches in [0031] that the work function layer is formed of doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. References Huang, Cheng and Chien are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang and Cheng with the specified features of Chien because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang, Cheng and Chien so that the work function layer is formed of doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium as taught by Chien in Huang’s and Cheng’s device since, this is commonly used work function tuning material. Regarding Claim 6, Huang, Cheng and Chien disclose: The semiconductor device of claim 5, The limitation “wherein the work function layer is formed by a deposition process and a subsequent etch-back process” in claim 6 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in “product by process” claim or not . 07-21-aia AIA Claim (s) 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Cheng and further in view of Lai et al (US 2023/0328970 A1 hereinafter Lai) . Regarding Claim 7, Huang and Cheng disclose: The semiconductor device of claim 2. Huang and Cheng do not disclose: wherein the first conductive layer is formed of germanium. However, Lai in a similar device teaches in Claim 18 that the first conductive layer is formed of germanium. References Huang, Cheng and Lai are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Huang and Cheng with the specified features of Lai because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Huang, Cheng and Lai so that the first conductive layer is formed of germanium as taught by Lai in Huang’s, Cheng’s device since, this is commonly used gate material. Regarding Claim 8, Huang, Cheng and Lai: The semiconductor device of claim 7, The limitation “wherein the first conductive layer is formed by a deposition process” in claim 8 is taken to be a product by process limitation, it is the patentability of the claimed product and not of recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product-by process claim, a rejection based on sections 102 or 103 is fair. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324,326(CCPA 1974); In re Marosi et al., 218 USPQ 289,292 (Fed. Cir. 1983); and particularly In re Thorpe, 227 USPQ 964,966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old or obvious product produced by a new method is not a patentable product, whether claim in “product by process” claim or not. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NISHATH YASMEEN/Primary Examiner, Art Unit 2811 Application/Control Number: 18/443,733 Page 2 Art Unit: 2811 Application/Control Number: 18/443,733 Page 3 Art Unit: 2811 Application/Control Number: 18/443,733 Page 4 Art Unit: 2811 Application/Control Number: 18/443,733 Page 5 Art Unit: 2811 Application/Control Number: 18/443,733 Page 6 Art Unit: 2811 Application/Control Number: 18/443,733 Page 7 Art Unit: 2811 Application/Control Number: 18/443,733 Page 8 Art Unit: 2811 Application/Control Number: 18/443,733 Page 9 Art Unit: 2811 Application/Control Number: 18/443,733 Page 10 Art Unit: 2811 Application/Control Number: 18/443,733 Page 11 Art Unit: 2811 Application/Control Number: 18/443,733 Page 12 Art Unit: 2811 Application/Control Number: 18/443,733 Page 13 Art Unit: 2811 Application/Control Number: 18/443,733 Page 14 Art Unit: 2811 Application/Control Number: 18/443,733 Page 15 Art Unit: 2811 Application/Control Number: 18/443,733 Page 16 Art Unit: 2811
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